J. Semicond. > 2016, Volume 37 > Issue 5 > 054002, doi: 10.1088/1674-4926/37/5/054002
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SEMICONDUCTOR DEVICES

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications

Pranav Kumar Asthana1, Yogesh Goswami1 and Bahniman Ghosh1, 2

+ Author Affiliations

 Corresponding author: pranava@iitk.ac.in; bghosh@utexas.edu

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Abstract: We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs (having low leakage) are improved by junctionless TFETs through blending advantages of Junctionless FETs (with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in IOFF of ～ 9 × 10-16A/μm, ION of ～20 μA/μm, ION/IOFF of ～2 × 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Key words: band-to-band tunneling (BTBT), tunnel field effect transistor (TFET), junctionless tunnel field effect transistor (JLTFET), ION/IOFF ratio, low power



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Fig. 1.  Cross sectional view of device structure,20 nm intrinsic channel single gate tunnel field effect transistor.

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Fig. 2.  Electron and hole concentration profile of iSG-TFET as function of position along the $x$-direction in (a) OFF state ($V_{\rm DS}=0.2$ V,$V_{\rm GS}=0$ V) (b) ON state ($V_{\rm DS}=0.2$ V,$V_{\rm GS}=0.2$ V) at the channel and dielectric interface (top).

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Fig. 3.  Lateral electric field of iSG-TFET as a function of the position along the $x$-direction in OFF state ($V_{\rm DS}=0.2$ V,$V_{\rm GS}=0$ V) and ON state ($V_{\rm DS}= 0.2$ V,$V_{\rm GS}=0.$2 V) at the channel and dielectric interface (top).

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Fig. 4.  Drain current versus Gate voltage of iSG-TFET at a drain voltage of 0.005 to 0.2 V,$\varepsilon_{\rm dielectric}$ of 29,$\varepsilon_{\rm spacer}$ of 3.9 and $T_{\rm SP}$ of 10 nm.

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Fig. 5.  Transconductance,$G_{\rm m}$ versus $V_{\rm GS}$ of \,iSG-TFET at $V_{\rm DS}$ from 0.005 to 0.2 V,$\varepsilon_{\rm dielectric}$ of 29,$\varepsilon_{\rm spacer}$ of 3.9 and $T_{\rm SP}$ of 10 nm.

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Fig. 6.  ON state current and ratio of ON and OFF state currents with respect to gate insulator dielectric constant of iSG-TFET at supply voltage of 0.2 V,$\varepsilon_{\rm spacer}$ of 3.9 and $T_{\rm SP}$ of 10 nm.

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Fig. 7.  ON state current and ratio of ON and OFF state current with respect to source and drain side spacer thickness of iSG-TFET at a supply voltage of 0.2 V,$\varepsilon_{\rm dielectric}$ of 29 and $\varepsilon_{\rm spacer}$ of 3.9.

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Fig. 8.  Drain current versus gate voltage with SiO$_{2}$ (3.9),Si$_{3}$N$_{4}$ (7.5),HfO$_{2}$ (29) and TiO$_{2}$ (80) as spacer dielectric at $V_{\rm DS}=0.2$ V,$\varepsilon_{\rm dielectric}$ of 29 and $T_{\rm SP}$ of 10 nm.

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Fig. 9.  Variation of capacitances,$C_{\rm GD}$ and $C_{\rm GS}$ in iSG-TFET with gate voltage at $V_{\rm DS}=0.2$ V,small signal voltage of 5 mV and frequency of 1 MHz,$\varepsilon_{\rm dielectric}$ of 29,$\varepsilon_{\rm spacer}$ of 3.9 and $T_{\rm SP}$ of 10 nm.

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    Received: 06 September 2015 Revised: Online: Published: 01 May 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(5): 054002
      Pranav Kumar Asthana, Yogesh Goswami, Bahniman Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications[J]. Journal of Semiconductors, 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002 P K Asthana, Y Goswami, B Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications[J]. J. Semicond., 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002.Export: BibTex EndNote
      Citation:
      Pranav Kumar Asthana, Yogesh Goswami, Bahniman Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications[J]. Journal of Semiconductors, 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002

      P K Asthana, Y Goswami, B Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications[J]. J. Semicond., 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002.
      Export: BibTex EndNote
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      A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications

      doi: 10.1088/1674-4926/37/5/054002
      • 1.

        Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

      • 2.

        Microelectronics Research Center, University of Texas at Austin, Austin, TX, 78758, USA

      More Information
      • Corresponding author: pranava@iitk.ac.in; bghosh@utexas.edu
      • Received Date: 2015-09-06
      • Accepted Date: 2015-11-17
      • Published Date: 2016-01-25

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