Abstract: The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width, line spacing and metal density. A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process. By checking test data such as field height, array height, step height and SEM photos, some conclusions are made. Line width is a critical factor of topographical shapes such as the step height and height difference. After the electroplating process, the fine line has a thicker copper thickness, while the wide line has the greatest step height. Three typical topographies, conformal-fill, supper-fill and over-fill, are observed. Moreover, quantified effects are found using the test data and explained by theory, which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.

Key words: ULSI