| Citation: |
Yuan Quan, Yang Haigang, Dong Fangyuan, Zhong Lungui. A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer[J]. Journal of Semiconductors, 2008, In Press.
Yuan Q, Yang H G, Dong F Y, Zhong L G. A \'Time Reuse\' Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer[J]. J. Semicond., 2008, 29(4): 794.
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A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer
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Abstract
A low power,continuous phase-switching multi-modulus divider is proposed based on the "time reuse" method.The novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so that the multi-modulus divider can work with higher input frequency and obtain the maximum modulus for a low power supply.According to the measurement results,this multi-modulus divider can divide the 2.4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V in a 0.35μm CMOS process.The maximum power dissipation is only 4.85mW.Compared with other CMOS multi-modulus dividers reported recently,our design demonstrates a considerable improvement in the power-to-speed ratio.-
Keywords:
- multi-modulus divider,
- phase-switching,
- low power,
- time reuse
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References
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