SEMICONDUCTOR INTEGRATED CIRCUITS

A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS

Qi Zhao1, Ran Li1, Dong Qiu1, Ting Yi1, , Yang Liu Bill2 and Zhiliang Hong1

+ Author Affiliations

 Corresponding author: Yi Ting, Email:yiting@fudan.edu.cn

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Abstract: A programmable 14-bit 1-GS/s current-steering digital-to-analog converter is presented. It features a selectable interpolation rate (2x/4x/8x) with a programmable interpolation filter. To improve the high-frequency performance, a "fast switching" technique that adds additional biasing to the current-switch is adopted. The data-dependent clock loading effect is also minimized with an improved switch control by using a double latch. This DAC is implemented in 65 nm CMOS technology with an active area of 1.56 mm2. The measured SFDRs are 70.05 dB at 250 MS/s for 120.65 MHz input sine-wave signal and 64.24 dB at 960 MS/s for 56.3 MHz input sine-wave signal, respectively.

Key words: DAChigh speedhigh resolutionprogrammable



[1]
Huang Q, Francese P A, Martelli C, et al. A 200 MS/s 14 b 97 mW DAC in 0.18μm CMOS. ISSCC Dig Tech Papers, 2004:364 doi: 10.1007/978-3-642-31229-8_6/fulltext.html
[2]
Chan K L, Galton L. A 14 b 100 MS/s DAC with fully segmented dynamic element matching. ISSCC Dig Tech Papers, 2006:582
[3]
Tseng W H. A 12 b 1.25 GS/s DAC in 90 nm CMOS with >70 dB SFDR up to 500 MHz. ISSCC Dig Tech Papers, 2011:192 http://www.wenkuxiazai.com/doc/1ae59ba226fff705cd170a3f.html
[4]
Tseng W H, Wu J T, Chu Y C. A CMOS 8-bit 1.6-GS/s DAC with digital random return to zero. IEEE Trans Circuits Syst I, 2011, 58(1):1 doi: 10.1109/TCSI.2010.2097652
[5]
Van den Bosch A, Borremans M A F, Steyaert M S J, et al. A 10-ewpage bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J Solid-State Circuits, 2001, 36(3):315 doi: 10.1109/4.910469
[6]
Lin C H, van der Goes F M L, Westra J R, et al. A 12 bit 2.9 GS/s DAC with IM3<-60 dBc beyond 1 GHz in 65 nm CMOS. IEEE J Solid-State Circuits, 2009, 44(12):3285 doi: 10.1109/JSSC.2009.2032624
[7]
Palimers P, Steyaert M S J. A 10-bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS. IEEE Trans Circuits Syst I, 2010, 57(11):2870 doi: 10.1109/TCSI.2010.2052491
[8]
Mercer D A. Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18μm CMOS. IEEE J Solid-State Circuits, 2007, 42(8):1688 doi: 10.1109/JSSC.2007.900279
[9]
Schafferer B, Adams R. A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications. ISSCC Dig Tech Papers, 2004:360 doi: 10.1007/978-3-642-31600-5_60
[10]
Cong Y, Geiger R L. Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Trans Circuits Syst I, 2000, 47(7):589 http://www.oalib.com/paper/1520860
Fig. 1.  Block diagram of the proposed DAC.

Fig. 2.  Frequency response of (a) HBF1, (b) HBF2 and (c) HBF3.

Fig. 3.  Block diagram of the interpolation filter HBF.

Fig. 4.  Block diagram of the DAC core.

Fig. 5.  Ideal switched current cell and simple model for analysis.

Fig. 6.  Current source structure.

Fig. 7.  Double latches with symmetrical decoding.

Fig. 8.  Current cell switch timing.

Fig. 9.  Switch driver circuit.

Fig. 10.  Floor plan for MSB and ULSB current sources.

Fig. 11.  Clock signal and output signal routing.

Fig. 12.  Microphotograph of the proposed DAC.

Fig. 13.  DNL & INL.

Fig. 14.  Output spectra at (a) $f_{\rm sample}$ $=$ 250 MHz, $f_{\rm in}$ $=$ 120.65 MHz, (b) $f_{\rm sample}$ $=$ 960 MHz, $f_{\rm in}$ $=$ 5 MHz, and (c) $f_{\rm sample}$ $=$ 960 MHz, $f_{\rm in}$ $=$ 56.3 MHz.

Table 1.   Performance of each filter.

Table 2.   DAC performance summary.

Table 3.   SFDR performance summary.

Table 4.   DAC performance comparison.

[1]
Huang Q, Francese P A, Martelli C, et al. A 200 MS/s 14 b 97 mW DAC in 0.18μm CMOS. ISSCC Dig Tech Papers, 2004:364 doi: 10.1007/978-3-642-31229-8_6/fulltext.html
[2]
Chan K L, Galton L. A 14 b 100 MS/s DAC with fully segmented dynamic element matching. ISSCC Dig Tech Papers, 2006:582
[3]
Tseng W H. A 12 b 1.25 GS/s DAC in 90 nm CMOS with >70 dB SFDR up to 500 MHz. ISSCC Dig Tech Papers, 2011:192 http://www.wenkuxiazai.com/doc/1ae59ba226fff705cd170a3f.html
[4]
Tseng W H, Wu J T, Chu Y C. A CMOS 8-bit 1.6-GS/s DAC with digital random return to zero. IEEE Trans Circuits Syst I, 2011, 58(1):1 doi: 10.1109/TCSI.2010.2097652
[5]
Van den Bosch A, Borremans M A F, Steyaert M S J, et al. A 10-ewpage bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J Solid-State Circuits, 2001, 36(3):315 doi: 10.1109/4.910469
[6]
Lin C H, van der Goes F M L, Westra J R, et al. A 12 bit 2.9 GS/s DAC with IM3<-60 dBc beyond 1 GHz in 65 nm CMOS. IEEE J Solid-State Circuits, 2009, 44(12):3285 doi: 10.1109/JSSC.2009.2032624
[7]
Palimers P, Steyaert M S J. A 10-bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS. IEEE Trans Circuits Syst I, 2010, 57(11):2870 doi: 10.1109/TCSI.2010.2052491
[8]
Mercer D A. Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18μm CMOS. IEEE J Solid-State Circuits, 2007, 42(8):1688 doi: 10.1109/JSSC.2007.900279
[9]
Schafferer B, Adams R. A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications. ISSCC Dig Tech Papers, 2004:360 doi: 10.1007/978-3-642-31600-5_60
[10]
Cong Y, Geiger R L. Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Trans Circuits Syst I, 2000, 47(7):589 http://www.oalib.com/paper/1520860
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    Received: 19 June 2012 Revised: 06 September 2012 Online: Published: 01 February 2013

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      Qi Zhao, Ran Li, Dong Qiu, Ting Yi, Yang Liu Bill, Zhiliang Hong. A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS[J]. Journal of Semiconductors, 2013, 34(2): 025004. doi: 10.1088/1674-4926/34/2/025004 Q Zhao, R Li, D Qiu, T Yi, Y L Bill, Z L Hong. A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS[J]. J. Semicond., 2013, 34(2): 025004. doi: 10.1088/1674-4926/34/2/025004.Export: BibTex EndNote
      Citation:
      Qi Zhao, Ran Li, Dong Qiu, Ting Yi, Yang Liu Bill, Zhiliang Hong. A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS[J]. Journal of Semiconductors, 2013, 34(2): 025004. doi: 10.1088/1674-4926/34/2/025004

      Q Zhao, R Li, D Qiu, T Yi, Y L Bill, Z L Hong. A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS[J]. J. Semicond., 2013, 34(2): 025004. doi: 10.1088/1674-4926/34/2/025004.
      Export: BibTex EndNote

      A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS

      doi: 10.1088/1674-4926/34/2/025004
      Funds:

      Project supported by the National High Technology Research and Development Program of China (No. 2009AA011605) and the National Natural Science Foundation of China (No. 61076027)

      the National Natural Science Foundation of China 61076027

      the National High Technology Research and Development Program of China 2009AA011605

      More Information
      • Corresponding author: Yi Ting, Email:yiting@fudan.edu.cn
      • Received Date: 2012-06-19
      • Revised Date: 2012-09-06
      • Published Date: 2013-02-01

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