| Citation: |
Lou Wenfeng, Feng Peng, Wang Haiyong, Wu Nanjian. Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer[J]. Journal of Semiconductors, 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004
Lou W F, Feng P, Wang H Y, Wu N J. Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer[J]. J. Semicond., 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004.
Export: BibTex EndNote
|
Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer
doi: 10.1088/1674-4926/33/4/045004
-
Abstract
A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than-52 dBc. The whole frequency synthesizer consumes only 4.35 mA@1.8 V.-
Keywords:
- phase-locked loop
-
References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] -
Proportional views
DownLoad: