Chin. J. Semicond. > 2006, Volume 27 > Issue 2 > 258-265

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Fine-Grain Sleep Transistor Insertion for Leakage Reduction

Yang Huazhong, Wang Yu, Lin Hai, Luo Rong and Wang Hui

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Abstract: A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming (MLP) problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.

Key words: leakage current reduction fine-grain sleep transistor insertion delay model mixed-integer linear programming

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    Received: 20 August 2015 Revised: Online: Published: 01 February 2006

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      Yang Huazhong, Wang Yu, Lin Hai, Luo Rong, Wang Hui. Fine-Grain Sleep Transistor Insertion for Leakage Reduction[J]. Journal of Semiconductors, 2006, In Press. Yang H Z, Wang Y, Lin H, Luo R, Wang H. Fine-Grain Sleep Transistor Insertion for Leakage Reduction[J]. Chin. J. Semicond., 2006, 27(2): 258.Export: BibTex EndNote
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      Yang Huazhong, Wang Yu, Lin Hai, Luo Rong, Wang Hui. Fine-Grain Sleep Transistor Insertion for Leakage Reduction[J]. Journal of Semiconductors, 2006, In Press.

      Yang H Z, Wang Y, Lin H, Luo R, Wang H. Fine-Grain Sleep Transistor Insertion for Leakage Reduction[J]. Chin. J. Semicond., 2006, 27(2): 258.
      Export: BibTex EndNote

      Fine-Grain Sleep Transistor Insertion for Leakage Reduction

      • Received Date: 2015-08-20

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