SEMICONDUCTOR INTEGRATED CIRCUITS

Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods

Dan Ren1, 2, Xiaoyu Xu1, , Hui Qu3 and Zhuoxiang Ren1

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 Corresponding author: Xiaoyu Xu, E-mail: xuxiaoyu@ime.ac.cn

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Abstract: Capacitance extraction is one of the key issues in integrated circuits and also a typical electrostatic problem. The dual discrete geometric method (DGM) is investigated to provide relative solutions in two-dimensional unstructured mesh space. The energy complementary characteristic and quick field energy computation thereof based on it are emphasized. Contrastive analysis between the dual finite element methods and the dual DGMs are presented both from theoretical derivation and through case studies. The DGM, taking the scalar potential as unknown on dual interlocked meshes, with simple form and good accuracy, is expected to be one of the mainstreaming methods in associated areas.

Key words: capacitance extractiondual discrete geometric methodsenergy complementaryelectrostatic field



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Fig. 1.  Interlocked primal mesh $M_{\rm P}$ and dual mesh $ M_{\rm D}$, corresponding equivalent capacitances networks, and unknown physical quantities utilized by dual FEMs and dual DGMs.

Fig. 2.  Prebuilt links and cuts utilized in the dual formulation of the FEM in terms of vector potential.

Fig. 3.  Elementary contributions to the primal and dual constitutive matrices.

Fig. 4.  Two-dimensional triangular element $e$ that consists of node $i$, $j$ and $k$, where $C^{e}_{ij}$ represents the elementary contribution of capacitance along edge $ij$.

Fig. 5.  (Color online) Model of cylindrical capacitor example. The inner radiuses of the two plates are respectively 0.1 $\mu$m and 0.9 $\mu$m. The relative permittivity of the dielectric between the plates is $\varepsilon _{\rm r}=3.70$. The mesh as shown consists of $3410$ nodes, $6658$ triangular elements and 10067 edges. The links prebuilt in the process of dual FEM are in the color of cyan. The inside plate and the outside plate are imposed 1 V and 0 V potential, respectively.

Fig. 6.  Results of analytical solution and numerical solutions with the DGM of cylindrical capacitor.

Fig. 7.  (Color online) Model of electrostatic system with multiple conductors, where the conductor $i$ is set as the main conductor and imposed 1~V potential, and other $11$ conductors are environmental conductors imposed 0 V potential. The unit of annotated geometric dimensions is $\mu$m. The computation domain that truncated is a square with side length 350 $\mu$m, where the conductors are centered. The instance of mesh as shown consists of $2536$ nodes, $4902$ triangles and $7437$ edges. The links among conductors built for dual FEM are shown in the cyan color.

Fig. 8.  Results and comparison of electrostatic energies with dual DGMs and dual FEMs along with the refinement of meshes. The energy bounds of both primal DGM and dual DGM are clearly observed.

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Table 1.   Results of energy with different methods for the example as shown in Figure 5 (unit of linear energy: $10^{-11}$ J/$\mu$m).

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Table 2.   Results of capacitance with different methods for the example as shown in Figure 7 (unit of linear capacitance: $10^{-1}$ fF/$\mu$m).

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    Received: 13 November 2014 Revised: Online: Published: 01 April 2015

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      Dan Ren, Xiaoyu Xu, Hui Qu, Zhuoxiang Ren. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods[J]. Journal of Semiconductors, 2015, 36(4): 045008. doi: 10.1088/1674-4926/36/4/045008 D Ren, X Y Xu, H Qu, Z X Ren. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods[J]. J. Semicond., 2015, 36(4): 045008. doi: 10.1088/1674-4926/36/4/045008.Export: BibTex EndNote
      Citation:
      Dan Ren, Xiaoyu Xu, Hui Qu, Zhuoxiang Ren. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods[J]. Journal of Semiconductors, 2015, 36(4): 045008. doi: 10.1088/1674-4926/36/4/045008

      D Ren, X Y Xu, H Qu, Z X Ren. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods[J]. J. Semicond., 2015, 36(4): 045008. doi: 10.1088/1674-4926/36/4/045008.
      Export: BibTex EndNote

      Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods

      doi: 10.1088/1674-4926/36/4/045008
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      Project supported by the National Science Foundation of China (No. 51207150), and the Director Foundation of Institute of Microelectronics of Chinese Academy of Sciences (Nos. Y2SF017001, Y3SZ0701).

      More Information
      • Corresponding author: E-mail: xuxiaoyu@ime.ac.cn
      • Received Date: 2014-11-13
      • Accepted Date: 2014-12-09
      • Published Date: 2015-01-25

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