SEMICONDUCTOR INTEGRATED CIRCUITS

Adder design using a 5-input majority gate in a novel "multilayer gate design paradigm" for quantum dot cellular automata circuits

Rohit Kumar1, Bahniman Ghosh1, 2 and Shoubhik Gupta3

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 Corresponding author: Bahniman Ghosh, E-mail: bghosh@utexas.edu

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Abstract: This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.

Key words: multilayer gate designQCAaddersMUX5-input majority voter



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Fig. 1.  Multilayer wire crossing.

Fig. 2.  The dark circles show the localization of electrons.

Fig. 3.  The ground state for the output cell under the influence of the driver cell.

Fig. 4.  Information flow in a clocked QCA wire.

Fig. 5.  (a) Inverter. (b) Majority gate.

Fig. 6.  Cell configuration in a multilayer.

Fig. 7.  The majority gate in the multilayer.

Fig. 8.  Previously proposed designs for 5-input majority gates.

Fig. 9.  The proposed 5-input majority gate in a multilayer.

Fig. 10.  Schematics of adders proposed in Reference [11, 22, 18], respectively.

Fig. 11.  (a) The layout of a 1-bit full adder in a single layer with multilayer wire crossing. (b) Simulation results.

Fig. 12.  (a) Layer-0. (b) Layer-1. (c) Layer-2. (d) Layer-3. (e) Layer-4. (f) Top view of the adder. (g) Simulation results.

Fig. 13.  (a) Layout of a 2-bit full adder in a single layer with multilayer wire crossing. (b) Simulation results.

Fig. 14.  (a) Layer-0. (b) Layer-1. (c) Layer-2. (d) Layer-3. (e) Layer-4. (f) Top view. (g) Simulation results.

Table 1.   Layer-wise analysis of the 1-bit full adders of Figures 11 and 12.

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Table 2.   Layer-wise analysis of the 2-bit adders of Figures 13 and 14.

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Table 3.   The comparison matrix for the 1-bit full adders of Figures 11 and 12.

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Table 4.   Correspondence value of MCy and yield.

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Table 5.   A comparison with 1-bit adders reported previously in the literature.

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    Received: 30 August 2014 Revised: Online: Published: 01 April 2015

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      Rohit Kumar, Bahniman Ghosh, Shoubhik Gupta. Adder design using a 5-input majority gate in a novel 'multilayer gate design paradigm' for quantum dot cellular automata circuits[J]. Journal of Semiconductors, 2015, 36(4): 045001. doi: 10.1088/1674-4926/36/4/045001 R Kumar, B Ghosh, S Gupta. Adder design using a 5-input majority gate in a novel \'multilayer gate design paradigm\' for quantum dot cellular automata circuits[J]. J. Semicond., 2015, 36(4): 045001. doi: 10.1088/1674-4926/36/4/045001.Export: BibTex EndNote
      Citation:
      Rohit Kumar, Bahniman Ghosh, Shoubhik Gupta. Adder design using a 5-input majority gate in a novel "multilayer gate design paradigm" for quantum dot cellular automata circuits[J]. Journal of Semiconductors, 2015, 36(4): 045001. doi: 10.1088/1674-4926/36/4/045001

      R Kumar, B Ghosh, S Gupta. Adder design using a 5-input majority gate in a novel \'multilayer gate design paradigm\' for quantum dot cellular automata circuits[J]. J. Semicond., 2015, 36(4): 045001. doi: 10.1088/1674-4926/36/4/045001.
      Export: BibTex EndNote

      Adder design using a 5-input majority gate in a novel "multilayer gate design paradigm" for quantum dot cellular automata circuits

      doi: 10.1088/1674-4926/36/4/045001
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      • Corresponding author: E-mail: bghosh@utexas.edu
      • Received Date: 2014-08-30
      • Accepted Date: 2014-11-12
      • Published Date: 2015-01-25

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