SEMICONDUCTOR DEVICES

3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET

Aadil T. Shora and Farooq A. Khanday

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 Corresponding author: Aadil T. Shora, Email: farooqkhanday@kashmiruniversity.ac.in

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Abstract: The evolution of the traditional metal oxide semiconductor field effect transistor (MOSFET) from planar single gate devices into 3D multiple gates has led to higher package density and high current drive. However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects (SCEs). In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented. The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model. The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

Key words: silicon-on-nothingshort channel effectsdual material gate; graded channel; trigate MOSFET



[1]
Emerging Research Devices. International technology roadmap for semiconductors. 2013
[2]
Kim Y B. Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater, 2010, 11: 93 doi: 10.4313/TEEM.2010.11.3.093
[3]
Xie Q, Xu J, Taur Y. Review and critique of analytic models of MOSFET short-channel effects in subthreshold. IEEE Trans Electron Devices, 2012, 59: 1569 doi: 10.1109/TED.2012.2191556
[4]
Riyadi M A, Suseno J E, Ismail R. The future of non-planar nanoelectronics MOSFET devices: a review. J Appl Sci, 2010, 10: 2136 doi: 10.3923/jas.2010.2136.2146
[5]
Balestra F, Cristoloveanu S, Benachir M, et al. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance. IEEE Electron Device Lett, 1987, 8: 410 doi: 10.1109/EDL.1987.26677
[6]
Ferain I, Collinge C A, Colinge J P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature, 2011, 479: 310 doi: 10.1038/nature10676
[7]
Doyle B S. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett, 2003, 24: 263 doi: 10.1109/LED.2003.810888
[8]
Guo Z B, Zhang J Y, Ye Z C, et al. 3-D analytical model for short-channel triple-gate junctionless MOSFETs. IEEE Trans Electron Devices, 2016, 63: 3857 doi: 10.1109/TED.2016.2598732
[9]
Liu H, Kuang Q, Luan S, et al. Performance analysis of dual-material gate SOI MOSFET. IEEE International Conference on Electron Devices and Solid-State Circuits, 2009
[10]
Ferhati H, Djeffal F. Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronics applications. J Comput Electron, 2018, 17: 129 doi: 10.1007/s10825-017-1052-1
[11]
Dutta P K, Bagga N, Naskar K et. al. Analysis and simulation of dual metal double gate SON MOSFET using hafnium dioxide for better performance. Michael Faraday IET International Summit 2015
[12]
Sharma A, Jain A, Pratap Y, et al. Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET. Solid-State Electron, 2016, 123: 26 doi: 10.1016/j.sse.2016.05.016
[13]
Monfray S, Skotnicki T, Fenouillet-Beranger C, et al. Emerging silicon-on-nothing (SON) devices technology. Solid-State Electron, 2013, 48: 887
[14]
Goel E. 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans Electron Devices, 2016, 63: 966 doi: 10.1109/TED.2016.2520096
[15]
Ghanatian H, Hosseini S E. Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs. J Comput Electron, 2016, 15: 508 doi: 10.1007/s10825-016-0817-2
[16]
Banerjee P, Sarkar S K. 3-D analytical modeling of dual-material triple-gate silicon-on-nothing MOSFET. IEEE Trans Electron Devices, 2017, 64: 368 doi: 10.1109/TED.2016.2643688
[17]
Francisco R, Isabel T, Godoy A, et al. Equivalent oxide thickness of trigate SOI MOSFETs with high-k insulators. IEEE Trans Electron Devices, 2009, 56: 2711 doi: 10.1109/TED.2009.2030713
[18]
Young K K. Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices, 1989, 36: 399 doi: 10.1109/16.19942
[19]
Bhattacharyya G. Comprehensive quantum mechanical modeling of short channel SON MOSFET with spatial composition grading of binary metal alloy gate electrode. Superlattices Microstruct, 2015, 83: 676 doi: 10.1016/j.spmi.2015.04.004
[20]
Ghanatian H, Hosseini S E. Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs. 23rd Iranian Conference on Electrical Engineering, 2015
[21]
Wu S H. Investigation of multi-Vth efficiency for trigate GeOI p-MOSFETs using analytical solution of 3-D Poisson’s equation. IEEE Trans Electron Devices, 2015, 62: 88 doi: 10.1109/TED.2014.2375871
[22]
Mohammadi H, Abdullah H, Dee C F. A modified two dimensional analytical model for short-channel fully depleted SOI MESFET's. Microelectron Reliab, 2018, 83: 173 doi: 10.1016/j.microrel.2018.03.004
[23]
Atlas User’s Manua. SILVACO Int. 2017
[24]
Karatsori T A, Theodorou C G, Haendler S. Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin BOX SOI MOSFETs suitable for circuit simulators. Microelectron Eng, 2016: 159: 9
[25]
Baral B, Das A K, De D, et al. An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short channel. Solid-State Electron, 2016, 29: 47
Fig. 1.  (Color online) 3-D schematic of gate-stack graded-channel dual material trigate MOSFET.

Fig. 2.  (Color online) Cross-sectional view of graded-channel gate-stack dual material trigate MOSFET.

Fig. 3.  (Color online) Surface potential distribution as a function of channel length. (a) Surface potential versus different gate oxide. (b) Surface potential distribution for conventional, DMG-, GC-, and DMG-GC- GS Trigate SON MOSFET as a function channel length.

Fig. 5.  (Color online) Variation of electric field along the channel for conventional, GCTG, DMTG, and GSGCDMT SON MOSFET.

Fig. 4.  (Color online) Surface potential distribution as a function of channel length for GSGCDMT SON MOSFET against different values of Vds.

Fig. 6.  (Color online) Threshold voltage variation as a function of channel length. (a) Threshold voltage variations for conventional, DMG-, GC-, and DMG-GC-GS Trigate SON MOSFET. (b) Threshold voltage variations for different gate oxides.

Fig. 7.  (Color online) DIBL comparison along the channel for DMG, GC, and DMG-GC GS-TG-SON MOSFET. The symbols in the graph represent the simulated values from TCAD for the proposed model.

Fig. 8.  (Color online) Subthreshold Swing comparison along the channel GC-, DMG-, and DMG-GC- GS-TG SON MOSFET. The symbols in the graph represent the simulated values from TCAD for the proposed model.

Table 1.   Employed device parameters.

Device structure ϕm1 (eV) ϕm2 (eV) Na1 (cm−3) Na2 (cm−3)
Conventional 4.8 4.8 1.5 × 1020 1.5 × 1020
DMG 4.8 4.4 1.5 × 1020 1.5 × 1020
GC 4.8 4.8 1.5 × 1020 1 × 1018
DMG-GC 4.8 4.4 1.5 × 1020 1 × 1018
DownLoad: CSV
[1]
Emerging Research Devices. International technology roadmap for semiconductors. 2013
[2]
Kim Y B. Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater, 2010, 11: 93 doi: 10.4313/TEEM.2010.11.3.093
[3]
Xie Q, Xu J, Taur Y. Review and critique of analytic models of MOSFET short-channel effects in subthreshold. IEEE Trans Electron Devices, 2012, 59: 1569 doi: 10.1109/TED.2012.2191556
[4]
Riyadi M A, Suseno J E, Ismail R. The future of non-planar nanoelectronics MOSFET devices: a review. J Appl Sci, 2010, 10: 2136 doi: 10.3923/jas.2010.2136.2146
[5]
Balestra F, Cristoloveanu S, Benachir M, et al. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance. IEEE Electron Device Lett, 1987, 8: 410 doi: 10.1109/EDL.1987.26677
[6]
Ferain I, Collinge C A, Colinge J P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature, 2011, 479: 310 doi: 10.1038/nature10676
[7]
Doyle B S. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett, 2003, 24: 263 doi: 10.1109/LED.2003.810888
[8]
Guo Z B, Zhang J Y, Ye Z C, et al. 3-D analytical model for short-channel triple-gate junctionless MOSFETs. IEEE Trans Electron Devices, 2016, 63: 3857 doi: 10.1109/TED.2016.2598732
[9]
Liu H, Kuang Q, Luan S, et al. Performance analysis of dual-material gate SOI MOSFET. IEEE International Conference on Electron Devices and Solid-State Circuits, 2009
[10]
Ferhati H, Djeffal F. Graded channel doping junctionless MOSFET: a potential high performance and low power leakage device for nanoelectronics applications. J Comput Electron, 2018, 17: 129 doi: 10.1007/s10825-017-1052-1
[11]
Dutta P K, Bagga N, Naskar K et. al. Analysis and simulation of dual metal double gate SON MOSFET using hafnium dioxide for better performance. Michael Faraday IET International Summit 2015
[12]
Sharma A, Jain A, Pratap Y, et al. Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET. Solid-State Electron, 2016, 123: 26 doi: 10.1016/j.sse.2016.05.016
[13]
Monfray S, Skotnicki T, Fenouillet-Beranger C, et al. Emerging silicon-on-nothing (SON) devices technology. Solid-State Electron, 2013, 48: 887
[14]
Goel E. 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans Electron Devices, 2016, 63: 966 doi: 10.1109/TED.2016.2520096
[15]
Ghanatian H, Hosseini S E. Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs. J Comput Electron, 2016, 15: 508 doi: 10.1007/s10825-016-0817-2
[16]
Banerjee P, Sarkar S K. 3-D analytical modeling of dual-material triple-gate silicon-on-nothing MOSFET. IEEE Trans Electron Devices, 2017, 64: 368 doi: 10.1109/TED.2016.2643688
[17]
Francisco R, Isabel T, Godoy A, et al. Equivalent oxide thickness of trigate SOI MOSFETs with high-k insulators. IEEE Trans Electron Devices, 2009, 56: 2711 doi: 10.1109/TED.2009.2030713
[18]
Young K K. Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Devices, 1989, 36: 399 doi: 10.1109/16.19942
[19]
Bhattacharyya G. Comprehensive quantum mechanical modeling of short channel SON MOSFET with spatial composition grading of binary metal alloy gate electrode. Superlattices Microstruct, 2015, 83: 676 doi: 10.1016/j.spmi.2015.04.004
[20]
Ghanatian H, Hosseini S E. Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs. 23rd Iranian Conference on Electrical Engineering, 2015
[21]
Wu S H. Investigation of multi-Vth efficiency for trigate GeOI p-MOSFETs using analytical solution of 3-D Poisson’s equation. IEEE Trans Electron Devices, 2015, 62: 88 doi: 10.1109/TED.2014.2375871
[22]
Mohammadi H, Abdullah H, Dee C F. A modified two dimensional analytical model for short-channel fully depleted SOI MESFET's. Microelectron Reliab, 2018, 83: 173 doi: 10.1016/j.microrel.2018.03.004
[23]
Atlas User’s Manua. SILVACO Int. 2017
[24]
Karatsori T A, Theodorou C G, Haendler S. Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin BOX SOI MOSFETs suitable for circuit simulators. Microelectron Eng, 2016: 159: 9
[25]
Baral B, Das A K, De D, et al. An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short channel. Solid-State Electron, 2016, 29: 47
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    Received: 27 June 2018 Revised: 28 July 2018 Online: Uncorrected proof: 19 September 2018Published: 13 December 2018

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      Aadil T. Shora, Farooq A. Khanday. 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET[J]. Journal of Semiconductors, 2018, 39(12): 124016. doi: 10.1088/1674-4926/39/12/124016 A T Shora, F A Khanday, 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET[J]. J. Semicond., 2018, 39(12): 124016. doi: 10.1088/1674-4926/39/12/124016.Export: BibTex EndNote
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      Aadil T. Shora, Farooq A. Khanday. 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET[J]. Journal of Semiconductors, 2018, 39(12): 124016. doi: 10.1088/1674-4926/39/12/124016

      A T Shora, F A Khanday, 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET[J]. J. Semicond., 2018, 39(12): 124016. doi: 10.1088/1674-4926/39/12/124016.
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      3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET

      doi: 10.1088/1674-4926/39/12/124016
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      Project supported by the Ministry of Electronics and Information Technology (MEITy), Govt. of India under its Visvesvaraya PhD Scheme (PhD-MLA/4(55)/2015-16).

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