SEMICONDUCTOR INTEGRATED CIRCUITS

Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

Zhan Gao1, 2, 3, Dan Ren1, 3, Shuai Yan1, 3, , Xiaoyu Xu1, 3 and Zhuoxiang Ren1, 3

+ Author Affiliations

 Corresponding author: Yan Shuai: Email: yanshuai@ime.ac.cn

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Abstract: Sensitivity analysis methods help to deal with the challenges of process variation in extraction of parasitic capacitances in an integrated circuit. The dual discrete geometric methods (DGMs), which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sensitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.

Key words: capacitance extractiondual discrete geometric methods (DGMs)process variationsensitivity analysis



[1]
International technology roadmap for semiconductors (ITRS) reports 2013. http://www.itrs.net, 2014
[2]
Gu Weiru, Ye Fan, Ren Junyan. An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation. Journal of Semiconductors, 2014, 35(8): 085006 doi: 10.1088/1674-4926/35/8/085006
[3]
Ren X, Pang C, Qin Z, et al. Design, analysis and test of high-frequency interconnections in 2.5D package with silicon interposer. Journal of Semiconductors, 2016, 37(4): 045003 doi: 10.1088/1674-4926/37/4/045003
[4]
Yu W, Zhuang H, Zhang C, et al. RWCap: a floating random walk solver for 3-D capacitance extraction of VLSI interconnects. IEEE Trans Comput-Aided Design, 2013, 32(3): 353 doi: 10.1109/TCAD.2012.2224346
[5]
Nabors K, White J. FastCap: a multipole accelerated 3-D capacitance extraction program. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1991, 10(11): 1447 doi: 10.1109/43.97624
[6]
Zhu Z, White J, Demir A. A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004: 887
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Hou J, Wang Z, Hong X. The hierarchical h-adaptive 3D boundary element computation of VLSI interconnect capacitance. Proceeding of the Asia South Pacific Design Automation Conference (ASP-DAC), 1999: 93 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.494.9270
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Chen G, Zhu H, Cui T, et al. ParAFEMCap: a parallel adaptive finite-element method for 3-D VLSI interconnect capacitance extraction. IEEE Trans Microw Theory Tech, 2012, 60(2): 218 doi: 10.1109/TMTT.2011.2176137
[10]
Specogna R. Extraction of VLSI multiconductor transmission line parameters by complementarity. IEEE Trans Very Large Scale Integr Syst, 2014, 22(1): 146 doi: 10.1109/TVLSI.2012.2232320
[11]
Bossavit A. Computational electromagnetism, variational formulations, complementarity, edge elements. New York: Academic Press, 1997
[12]
Ren Z, Xu X. Dual discrete geometric methods in terms of scalar potential on unstructured mesh in electrostatics. IEEE Trans Magnet, 2014, 50(2): 37 doi: 10.1109/TMAG.2013.2280452
[13]
Ren Dan, Xu Xiaoyu, Qu Hui, et al. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods. Journal of Semiconductors, 2015, 36(4): 045008 doi: 10.1088/1674-4926/36/4/045008
[14]
Hirani A N. Discrete exterior calculus. PhD thesis, California Institute of Technology, 2003 http://cn.bing.com/academic/profile?id=2120103450&encoded=0&v=paper_preview&mkt=zh-cn
[15]
Specogna R. Complementary geometric formulations for electrostatics. International Journal for Numerical Methods in Engineering, 2011, 86(8): 1041 doi: 10.1002/nme.v86.8
[16]
Ren Z. A 3-D vector potential formulation using edge element for electrostatic field computation. IEEE Trans Magnet, 1995, 31: 1520 doi: 10.1109/20.376319
[17]
Xu X, Ren Z, Qu H, Ren D. 3-D IC interconnect capacitance extraction using dual discrete geometric methods with prism elements. IEEE Trans Very Large Scale Integr Syst, 2016, 24(4): 1524 doi: 10.1109/TVLSI.2015.2459043
[18]
El-Moselhy A T, Elfadel I M, Daniel L. A capacitance solver for incremental variation-aware extraction. IEEE/ACM International Conference on Date of Conference Computer-Aided Design, ICCAD 2008: 662 http://cn.bing.com/academic/profile?id=1903428531&encoded=0&v=paper_preview&mkt=zh-cn
[19]
Yu B, Kolk K J, Meijs N P. Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. IEEE Custom Integrated Circuits Conference CICC, 2009: 423 http://cn.bing.com/academic/profile?id=2138889479&encoded=0&v=paper_preview&mkt=zh-cn
[20]
Qu H, Kong L, Xu Y, et al. Finite-element computation of sensitivities of interconnect parasitic capacitances to the process variation in VLSI. IEEE Trans Magnet, 2008, 44(8): 1386 http://cn.bing.com/academic/profile?id=2096056818&encoded=0&v=paper_preview&mkt=zh-cn
[21]
Bossavit A. How weak is the "weak solution" in finite element methods. IEEE Trans Magnet, 1998, 34(5): 2429 doi: 10.1109/20.717558
[22]
Ren Z, Xu X. Computation of second order capacitance sensitivity using adjoint method in finite element modeling. IEEE Trans Magnet, 2012, 48(2): 231 doi: 10.1109/TMAG.2011.2172194
Fig. 1.  (Color online) Schematic diagram of the (a) interlock primal mesh and (c) dual mesh, (b) and (d) the corresponding equivalent capacitance networks, when taking two dimensional (2D) space as an example. The unknown physical quantities utilized by the dual DGMs are located, respectively, on the vertexes of the primal and dual meshes, which are denoted by hollow circles.

Fig. 2.  Relation of the primal-dual pair of sequences and meshes

Fig. 3.  Equivalent capacitances along the connections among vertexes, i.e., edges, of the primal mesh and the dual mesh, and the elementary contributions of the neighbour elements. As shown in (a), $\sigma$ is the length of the edge shared by the element ${e_i}$ and element ${e_j}$ , $ \sigma^{*}=\sigma^{*}_{i}+\sigma^{*}_{j}$ is the length of the edge of the dual mesh. $\sigma^{*}_{i}$ and $\sigma^{*}_{j}$ belong to ${e_i}$ and ${e_j}$ , respectively, as shown in (b). The relative dielectric constants of ${e_i}$ and ${e_j}$ are $\varepsilon_i$ and $\varepsilon_j$ , respectively. (c) and (e) show the capacitances C and $C^*$ imposed on edges of the primal mesh and the dual mesh, respectively. (d) and (f) show the elementary contributions ${C_i}$ and ${C_j}$ for C, and $C^*_i$ and $C^*_j$ for $C^*$ , respectively. As a note, ${C_i}$ and ${C_j}$ are in parallel connection, and $C^*_i$ and $C^*_j$ are in series connection.

Fig. 4.  (a) Triangular element and elemental contributions to the (b) primal matrix and (c) dual matrix, where O is the circumcenter of the triangle ijk, O’is the foot of the perpendicular on the edge jk, and also the midpoint on jk. ${\alpha _s}$ is the interior angle at node s where s=i, j, and k. The three capacitances in (b) are in delta ( $\Delta $ ) connection, and (c) star (Y) connection.

Fig. 5.  Treatment of boundaries, such as boundary of truncated computational domain denoted by $\mathit{\Gamma}_{e}$ in (a), and Dirichlet boundary denoted by $\mathit{\Gamma}_{c}$ in (b). For $\mathit{\Gamma}_{e}$ , extra vertexes, such as ${v_1}$ and ${v_2}$ , are appended as unknowns. For $\mathit{\Gamma}_{c}$ , since the conductor is a equipotential body, the elementary contribution of element ${e_j}$ , ${C_j}$ for the primal net and $C_j^*$ for the dual net are eliminated. That is, ${C_j}$ in (c) is set to zero (0) and $C_j^*$ in (d) is set to infinity ( $\infty$ ). For the dual net, ${v_j}$ is moved to ${v_{\left({ij} \right)}}$ , which is the intersection point of edge ${v_i}$ ${v_j}$ and boundary $\mathit{\Gamma}_{c}$ .

Fig. 6.  (Color online) Schematic diagram of boundary condition. Only part of the meshes are presented. The Dirichlet boundary conditions are imposed on $\mathit{\Gamma_{ei}}$ and $\mathit{\Gamma}_{ej}$ , i.e., the surfaces of conductor i and j. The Dirichlet nodes along the surfaces of conductor i and j are denoted by empty circles in black, and unknown nodes are denoted by dots in blue.

Fig. 7.  (Color online) Integration path { $\mathit{\Gamma} _{p}$ } and { $\mathit{\Gamma} _{d}$ } for electric flux computation in the case of (a) primal solution and (b) dual solution, respectively. Obviously, the flux can be obtained easily by summing up the flux inside each equivalent capacitance that connects to the boundary of the objective conductor.

Fig. 8.  Example model (not to scale) for interconnect capacitances with multiple conductors. In nominal condition, conductors 1, 2 and 3 have the same dimensions of 4 (line width W) $\times$ 4 μm2 (line thickness T), and the conductor 0 24 $\times$ 2 μm2. The distance between every two conductors is 2 μm, including the spacing S and D20. The dimensions of rectangle computation domain are 40 $\times$ 30 μm2, where the four conductors are centered. The relative permittivity of dielectric material surrounding the conductors is 3.70.

Fig. 9.  (Color online) Primal mesh (up) and corresponding dual mesh (down) of a 4-conductor electrostatic system. The primal mesh demonstrated consists of 883 nodes and 1668 triangular elements. The dual mesh is constructed through circumcenter from the primal mesh. Only part of the computation domain is shown.

Fig. 10.  (Color online) (a) The primal and dual results and (b) the average results of capacitance calculated by field solver directly and estimated by first order sensitivities with respect to the variation of the line width W.

Fig. 11.  (Color online) (a) The primal and dual results and (b) the average results of capacitance calculated by field solver directly and estimated by first order sensitivities with respect to the variation of the line thickness $\Delta $ T.

Fig. 12.  (Color online) Absolute magnitude of relative errors of capacitance sensitivity of $C_{22}$ between results calculated by field solver and by sensitivities with respect to the variation of the (a) line width $\Delta W$ and (b) line thickness $\Delta T$ , in case of the primal, dual and average solutions.

Fig. 13.  (Color online) Absolute magnitude of relative errors of capacitance sensitivity of ${C_{20}}$ , ${C_{21}}$ , and ${C_{22}}$ between results calculated by field solver and by sensitivities with respect to the variation of the (a) line width $\Delta W$ and (b) line thickness $\Delta T$ , in case of the average solution.

Table 1.   Results of capacitance sensitivity with respect to line width W and line thickness T using the primal, dual and average methods. (unit: fF/μm2).

Table 2.   Comparison of capacitances calculated by field solver and by sensitivity at the nominal dimensions with the primal and dual solutions and their average, which is referred to average solution (unit: fF/μm).

[1]
International technology roadmap for semiconductors (ITRS) reports 2013. http://www.itrs.net, 2014
[2]
Gu Weiru, Ye Fan, Ren Junyan. An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation. Journal of Semiconductors, 2014, 35(8): 085006 doi: 10.1088/1674-4926/35/8/085006
[3]
Ren X, Pang C, Qin Z, et al. Design, analysis and test of high-frequency interconnections in 2.5D package with silicon interposer. Journal of Semiconductors, 2016, 37(4): 045003 doi: 10.1088/1674-4926/37/4/045003
[4]
Yu W, Zhuang H, Zhang C, et al. RWCap: a floating random walk solver for 3-D capacitance extraction of VLSI interconnects. IEEE Trans Comput-Aided Design, 2013, 32(3): 353 doi: 10.1109/TCAD.2012.2224346
[5]
Nabors K, White J. FastCap: a multipole accelerated 3-D capacitance extraction program. IEEE Trans Comput-Aided Des Integr Circuits Syst, 1991, 10(11): 1447 doi: 10.1109/43.97624
[6]
Zhu Z, White J, Demir A. A stochastic integral equation method for modeling the rough surface effect on interconnect capacitance. IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004: 887
[7]
Hou J, Wang Z, Hong X. The hierarchical h-adaptive 3D boundary element computation of VLSI interconnect capacitance. Proceeding of the Asia South Pacific Design Automation Conference (ASP-DAC), 1999: 93 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.494.9270
[8]
Shi W, Yu F. A divide-and-conquer algorithm for 3-D capacitance extraction. IEEE Trans Comput-Aided Des of Integr Circuits Syst, 2004, 23(8): 1157 doi: 10.1109/TCAD.2004.831595
[9]
Chen G, Zhu H, Cui T, et al. ParAFEMCap: a parallel adaptive finite-element method for 3-D VLSI interconnect capacitance extraction. IEEE Trans Microw Theory Tech, 2012, 60(2): 218 doi: 10.1109/TMTT.2011.2176137
[10]
Specogna R. Extraction of VLSI multiconductor transmission line parameters by complementarity. IEEE Trans Very Large Scale Integr Syst, 2014, 22(1): 146 doi: 10.1109/TVLSI.2012.2232320
[11]
Bossavit A. Computational electromagnetism, variational formulations, complementarity, edge elements. New York: Academic Press, 1997
[12]
Ren Z, Xu X. Dual discrete geometric methods in terms of scalar potential on unstructured mesh in electrostatics. IEEE Trans Magnet, 2014, 50(2): 37 doi: 10.1109/TMAG.2013.2280452
[13]
Ren Dan, Xu Xiaoyu, Qu Hui, et al. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods. Journal of Semiconductors, 2015, 36(4): 045008 doi: 10.1088/1674-4926/36/4/045008
[14]
Hirani A N. Discrete exterior calculus. PhD thesis, California Institute of Technology, 2003 http://cn.bing.com/academic/profile?id=2120103450&encoded=0&v=paper_preview&mkt=zh-cn
[15]
Specogna R. Complementary geometric formulations for electrostatics. International Journal for Numerical Methods in Engineering, 2011, 86(8): 1041 doi: 10.1002/nme.v86.8
[16]
Ren Z. A 3-D vector potential formulation using edge element for electrostatic field computation. IEEE Trans Magnet, 1995, 31: 1520 doi: 10.1109/20.376319
[17]
Xu X, Ren Z, Qu H, Ren D. 3-D IC interconnect capacitance extraction using dual discrete geometric methods with prism elements. IEEE Trans Very Large Scale Integr Syst, 2016, 24(4): 1524 doi: 10.1109/TVLSI.2015.2459043
[18]
El-Moselhy A T, Elfadel I M, Daniel L. A capacitance solver for incremental variation-aware extraction. IEEE/ACM International Conference on Date of Conference Computer-Aided Design, ICCAD 2008: 662 http://cn.bing.com/academic/profile?id=1903428531&encoded=0&v=paper_preview&mkt=zh-cn
[19]
Yu B, Kolk K J, Meijs N P. Sensitivity computation using domain-decomposition for boundary element method based capacitance extractors. IEEE Custom Integrated Circuits Conference CICC, 2009: 423 http://cn.bing.com/academic/profile?id=2138889479&encoded=0&v=paper_preview&mkt=zh-cn
[20]
Qu H, Kong L, Xu Y, et al. Finite-element computation of sensitivities of interconnect parasitic capacitances to the process variation in VLSI. IEEE Trans Magnet, 2008, 44(8): 1386 http://cn.bing.com/academic/profile?id=2096056818&encoded=0&v=paper_preview&mkt=zh-cn
[21]
Bossavit A. How weak is the "weak solution" in finite element methods. IEEE Trans Magnet, 1998, 34(5): 2429 doi: 10.1109/20.717558
[22]
Ren Z, Xu X. Computation of second order capacitance sensitivity using adjoint method in finite element modeling. IEEE Trans Magnet, 2012, 48(2): 231 doi: 10.1109/TMAG.2011.2172194
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    Received: 22 September 2015 Revised: 24 April 2016 Online: Published: 01 August 2016

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      Zhan Gao, Dan Ren, Shuai Yan, Xiaoyu Xu, Zhuoxiang Ren. Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods[J]. Journal of Semiconductors, 2016, 37(8): 085003. doi: 10.1088/1674-4926/37/8/085003 Z Gao, D Ren, S Yan, X Y Xu, Z X Ren. Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods[J]. J. Semicond., 2016, 37(8): 085003. doi: 10.1088/1674-4926/37/8/085003.Export: BibTex EndNote
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      Zhan Gao, Dan Ren, Shuai Yan, Xiaoyu Xu, Zhuoxiang Ren. Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods[J]. Journal of Semiconductors, 2016, 37(8): 085003. doi: 10.1088/1674-4926/37/8/085003

      Z Gao, D Ren, S Yan, X Y Xu, Z X Ren. Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods[J]. J. Semicond., 2016, 37(8): 085003. doi: 10.1088/1674-4926/37/8/085003.
      Export: BibTex EndNote

      Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

      doi: 10.1088/1674-4926/37/8/085003
      Funds:

      Project supported by the National Natural Science Foundation of China (Nos. 61574167, 51407181)

      National Natural Science Foundation of China 51407181

      National Natural Science Foundation of China 61574167

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      • Corresponding author: Yan Shuai: Email: yanshuai@ime.ac.cn
      • Received Date: 2015-09-22
      • Revised Date: 2016-04-24
      • Published Date: 2016-08-01

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