J. Semicond. > 2017, Volume 38 > Issue 7 > 074003, doi: 10.1088/1674-4926/38/7/074003
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SEMICONDUCTOR DEVICES

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

S.K. Vishvakarma, Ankur Beohar, Vikas Vijayvargiya and Priyal Trivedi

+ Author Affiliations

 Corresponding author: S. K. Vishvakarma, Email: skvishvakarma@iiti.ac.in

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Abstract: In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.

Key words: tunnel field effect transistor, cutoff frequency, maximum oscillation frequency, and gate all around



[1]
Abou-Allam E, Manku T, Ting M, et al. Impact of technology scaling on CMOS RF devices and circuits. IEEE Custom Integr Circuits Conf, 2000: 21 https://www.researchgate.net/publication/3852765_Impact_of_technology_scaling_on_CMOS_RF_devices_and_circuits
[2]
El Hamid H A, Guitart J R, Iniguez B. Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double gate MOSFETs. IEEE Trans Electron Devices, 2007, 54(6): 1402 doi: 10.1109/TED.2007.895856
[3]
Sun X, Lu Q, Moroz V, et al. Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap. IEEE Trans Electron Devices, 2008, 29(5): 491 doi: 10.1109/LED.2008.919795
[4]
Bangsaruntip S, Cohen G M, Majumdar A, et al. Universality of short channel effects in undoped-body silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2010, 31(9): 903 doi: 10.1109/LED.2010.2052231
[5]
Vishvakarm S K, Monga U, Fjeldly T A. Unified analytical modeling of GAA nanoscale MOSFETs. 10th IEEE Int Conf Solid-State Integr Circuit Technol, 2010: 1733 https://www.researchgate.net/publication/261349383_Unified_analytical_modeling_of_GAA_nanoscale_MOSFETs
[6]
Vishvakarma S K, Monga U, Fjeldly T A. Analytical modeling of the subthreshold electrostatics of nanoscale GAA square gate MOSFETs. Proceedings NSTI Nanotech Conference, Workshop on Compact Modeling, Anaheim, CA, USA, 2010: 789
[7]
Sharma D, Vishvakarma S K. Precise~analytical model for short channel quadruple gate-all-around MOSFET.IEEE Trans Nanotechnol, 2013, 12(3): 378 doi: 10.1109/TNANO.2013.2251895
[8]
Ionescu A M. New functionality and ultra low power: key opportunities for post-CMOS era. Proc Int Symp VLSI Technol Syst, 2008: 72 https://www.researchgate.net/publication/4337517_New_functionality_and_ultra_low_power_key_opportunities_for_post-CMOS_era
[9]
Bhuwalka K K, Sedlmaier S, Ludsteck A K, et al. Vertical tunnel field-effect transistor. IEEE Trans Electron Devices, 2004, 51(2): 279 doi: 10.1109/TED.2003.821575
[10]
Verhulst A S, Vandenberghe W G, Maex K, et al. Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett, 2007, 91(5): 05 https://www.researchgate.net/publication/230743631_Tunnel_field-effect_transistor_without_gate-drain_overlap
[11]
Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725 doi: 10.1109/TED.2007.899389
[12]
Cho S, Lee S J, Kim K, et al. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors. IEEE Trans Electron Devices, 2011, 58(12): 4164 doi: 10.1109/TED.2011.2167335
[13]
Vijayvargiya V, Vishvakarma S K. Effect of drain doping profile on double gate tunnel field effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol, 2014, 13: 974 doi: 10.1109/TNANO.2014.2336812
[14]
ATLAS User's Manual, Silvaco Int. , Santa Clara, CA, April 20, 2015
[15]
Enz C C, Vittoz E A. Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. New York: Wiely, 2016
[16]
Yang Y, Tong X, Yang L T, et al. Tunneling field-effect transistor: capacitance components and modeling. IEEE Electron Device Lett, 2010, 31(7): 752 doi: 10.1109/LED.2010.2047240
[17]
Iniguez B, Fjeldly T A, Lazaro A. Compact modeling solutions for nanoscale double gate and gate all around MOSFETs. IEEE Trans Electron Devices, 2006, 53 (9): 2128 doi: 10.1109/TED.2006.881007
[18]
Abou-Allam E, Manku T, Ting M, et al. Impact of technology scaling on CMOS RF devices and circuits. Proc IEEE Custom Integr Circuits Conf, 2000: 21 https://www.researchgate.net/publication/3852765_Impact_of_technology_scaling_on_CMOS_RF_devices_and_circuits
[19]
El Hamid H A, Guitart J R, Iniguez B. Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double gate MOSFETs. IEEE Trans Electron Devices 2007, 54 (6): 1402 doi: 10.1109/TED.2007.895856
[20]
Sun X, Lu Q, Moroz V, et al. Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap. IEEE Trans Electron Devices, 2008, 29(5): 491 doi: 10.1109/LED.2008.919795
[21]
Bangsaruntip S, Cohen G M, Majumdar A, et al. Universality of short channel effects in undoped-body silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2010, 31(9): 903 doi: 10.1109/LED.2010.2052231
[22]
Vishvakarma S K, Monga U, Fjeldly T A. Unified analytical modeling of GAA nanoscale MOSFETs. 10th IEEE Inte Conf Solid-State Integr Circuit Technol, 2010: 1733 https://www.researchgate.net/publication/261349383_Unified_analytical_modeling_of_GAA_nanoscale_MOSFETs
[23]
Vishvakarma S K, Monga U, Fjeldly T A. Analytical modeling of the subthreshold electrostatics of nanoscale GAA square gate MOSFETs. Proceedings NSTI Nanotech Conference, Workshop on Compact Modeling, Anaheim, CA, USA, 2010: 789
[24]
Sharma D, Vishvakarma S K. Precise~analytical model for short channel quadruple gate-all-around MOSFET. IEEE Trans Nanotechnol, 2013, 12(3): 378 doi: 10.1109/TNANO.2013.2251895
[25]
Ionescu A M. New functionality and ultra low power: key opportunities for post-CMOS era. In Proc Int Symp VLSI Technol Syst, 2008: 72 https://www.researchgate.net/publication/4337517_New_functionality_and_ultra_low_power_key_opportunities_for_post-CMOS_era
[26]
Bhuwalka K K, Sedlmaier S, Ludsteck A K, et al. Vertical tunnel field-effect transistor. IEEE Trans Electron Devices, 2004, 51(2): 279 doi: 10.1109/TED.2003.821575
[27]
Verhulst A S, Vandenberghe W G, Maex K, et al. Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett, 2007, 91(5): 53102 doi: 10.1063/1.2757593
[28]
Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725 doi: 10.1109/TED.2007.899389
[29]
Cho S, Lee J S, Kim K R, et al. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors. IEEE Trans Electron Devices, 2011, 58(12): 4164 doi: 10.1109/TED.2011.2167335
[30]
Vijayvargiya V, Vishvakarma S K. Effect of drain doping profile on double gate tunnel field effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol, 2014, 13(5): 974 doi: 10.1109/TNANO.2014.2336812
[31]
ATLAS User's Manual, Silvaco Int. , Santa Clara, CA, April 20, 2010
[32]
Enz C C, Vittoz E A. Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. New York: Wiely, 2006
Fig. 1.  (Color online) (a) 3D view of simulated cylindrical GAA-nTFET, and (b) cross-sectional view of cylindrical GAA-nTFET along z axis using 3D-TCAD.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  (Color online) (a) Ids–Vgs characteristics for GAA-TFET at different channel length, and (b) on-current values for different channel length at varying radius.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (Color online) Ids–Vgs characteristics of GAA-TFET for different radius on linear scale.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  (Color online) Transfer characteristic of gate capacitance values for GAA-TFET as a function of Vgs for different lengths at different radii. (a) Gate-drain capacitance. (b) Gate-source capacitance.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  (Color online) Transfer characteristics of transconductance and gate drain conduction for GAA-TFET as a function of Vgs. (a) For varying length. (b) For varying radius.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  (Color online) (a) Comparison for cut-off frequency, and (b) maximum oscillation frequency of GAA-TFET for different channel lengths at varying radii as a function of Vgs.

DownLoad: Full-Size Img PowerPoint

Table 1.   Comparison of device DC characteristics of GAA-TFET for different channel length.
DownLoad: CSV

Table 2.   Comparison of device gate capacitance of GAA-TFET for different channel length and radii.
DownLoad: CSV

Table 3.   Comparison of analog performance of DG-TFET for different channel length at different radii
DownLoad: CSV
[1]
Abou-Allam E, Manku T, Ting M, et al. Impact of technology scaling on CMOS RF devices and circuits. IEEE Custom Integr Circuits Conf, 2000: 21 https://www.researchgate.net/publication/3852765_Impact_of_technology_scaling_on_CMOS_RF_devices_and_circuits
[2]
El Hamid H A, Guitart J R, Iniguez B. Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double gate MOSFETs. IEEE Trans Electron Devices, 2007, 54(6): 1402 doi: 10.1109/TED.2007.895856
[3]
Sun X, Lu Q, Moroz V, et al. Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap. IEEE Trans Electron Devices, 2008, 29(5): 491 doi: 10.1109/LED.2008.919795
[4]
Bangsaruntip S, Cohen G M, Majumdar A, et al. Universality of short channel effects in undoped-body silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2010, 31(9): 903 doi: 10.1109/LED.2010.2052231
[5]
Vishvakarm S K, Monga U, Fjeldly T A. Unified analytical modeling of GAA nanoscale MOSFETs. 10th IEEE Int Conf Solid-State Integr Circuit Technol, 2010: 1733 https://www.researchgate.net/publication/261349383_Unified_analytical_modeling_of_GAA_nanoscale_MOSFETs
[6]
Vishvakarma S K, Monga U, Fjeldly T A. Analytical modeling of the subthreshold electrostatics of nanoscale GAA square gate MOSFETs. Proceedings NSTI Nanotech Conference, Workshop on Compact Modeling, Anaheim, CA, USA, 2010: 789
[7]
Sharma D, Vishvakarma S K. Precise~analytical model for short channel quadruple gate-all-around MOSFET.IEEE Trans Nanotechnol, 2013, 12(3): 378 doi: 10.1109/TNANO.2013.2251895
[8]
Ionescu A M. New functionality and ultra low power: key opportunities for post-CMOS era. Proc Int Symp VLSI Technol Syst, 2008: 72 https://www.researchgate.net/publication/4337517_New_functionality_and_ultra_low_power_key_opportunities_for_post-CMOS_era
[9]
Bhuwalka K K, Sedlmaier S, Ludsteck A K, et al. Vertical tunnel field-effect transistor. IEEE Trans Electron Devices, 2004, 51(2): 279 doi: 10.1109/TED.2003.821575
[10]
Verhulst A S, Vandenberghe W G, Maex K, et al. Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett, 2007, 91(5): 05 https://www.researchgate.net/publication/230743631_Tunnel_field-effect_transistor_without_gate-drain_overlap
[11]
Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725 doi: 10.1109/TED.2007.899389
[12]
Cho S, Lee S J, Kim K, et al. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors. IEEE Trans Electron Devices, 2011, 58(12): 4164 doi: 10.1109/TED.2011.2167335
[13]
Vijayvargiya V, Vishvakarma S K. Effect of drain doping profile on double gate tunnel field effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol, 2014, 13: 974 doi: 10.1109/TNANO.2014.2336812
[14]
ATLAS User's Manual, Silvaco Int. , Santa Clara, CA, April 20, 2015
[15]
Enz C C, Vittoz E A. Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. New York: Wiely, 2016
[16]
Yang Y, Tong X, Yang L T, et al. Tunneling field-effect transistor: capacitance components and modeling. IEEE Electron Device Lett, 2010, 31(7): 752 doi: 10.1109/LED.2010.2047240
[17]
Iniguez B, Fjeldly T A, Lazaro A. Compact modeling solutions for nanoscale double gate and gate all around MOSFETs. IEEE Trans Electron Devices, 2006, 53 (9): 2128 doi: 10.1109/TED.2006.881007
[18]
Abou-Allam E, Manku T, Ting M, et al. Impact of technology scaling on CMOS RF devices and circuits. Proc IEEE Custom Integr Circuits Conf, 2000: 21 https://www.researchgate.net/publication/3852765_Impact_of_technology_scaling_on_CMOS_RF_devices_and_circuits
[19]
El Hamid H A, Guitart J R, Iniguez B. Two dimensional analytical threshold voltage and subthreshold swing models of undoped symmetric double gate MOSFETs. IEEE Trans Electron Devices 2007, 54 (6): 1402 doi: 10.1109/TED.2007.895856
[20]
Sun X, Lu Q, Moroz V, et al. Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap. IEEE Trans Electron Devices, 2008, 29(5): 491 doi: 10.1109/LED.2008.919795
[21]
Bangsaruntip S, Cohen G M, Majumdar A, et al. Universality of short channel effects in undoped-body silicon nanowire MOSFETs. IEEE Trans Electron Devices, 2010, 31(9): 903 doi: 10.1109/LED.2010.2052231
[22]
Vishvakarma S K, Monga U, Fjeldly T A. Unified analytical modeling of GAA nanoscale MOSFETs. 10th IEEE Inte Conf Solid-State Integr Circuit Technol, 2010: 1733 https://www.researchgate.net/publication/261349383_Unified_analytical_modeling_of_GAA_nanoscale_MOSFETs
[23]
Vishvakarma S K, Monga U, Fjeldly T A. Analytical modeling of the subthreshold electrostatics of nanoscale GAA square gate MOSFETs. Proceedings NSTI Nanotech Conference, Workshop on Compact Modeling, Anaheim, CA, USA, 2010: 789
[24]
Sharma D, Vishvakarma S K. Precise~analytical model for short channel quadruple gate-all-around MOSFET. IEEE Trans Nanotechnol, 2013, 12(3): 378 doi: 10.1109/TNANO.2013.2251895
[25]
Ionescu A M. New functionality and ultra low power: key opportunities for post-CMOS era. In Proc Int Symp VLSI Technol Syst, 2008: 72 https://www.researchgate.net/publication/4337517_New_functionality_and_ultra_low_power_key_opportunities_for_post-CMOS_era
[26]
Bhuwalka K K, Sedlmaier S, Ludsteck A K, et al. Vertical tunnel field-effect transistor. IEEE Trans Electron Devices, 2004, 51(2): 279 doi: 10.1109/TED.2003.821575
[27]
Verhulst A S, Vandenberghe W G, Maex K, et al. Tunnel field-effect transistor without gate-drain overlap. Appl Phys Lett, 2007, 91(5): 53102 doi: 10.1063/1.2757593
[28]
Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725 doi: 10.1109/TED.2007.899389
[29]
Cho S, Lee J S, Kim K R, et al. Analyses on small-signal parameters and radio-frequency modeling of gate-all-around tunneling field-effect transistors. IEEE Trans Electron Devices, 2011, 58(12): 4164 doi: 10.1109/TED.2011.2167335
[30]
Vijayvargiya V, Vishvakarma S K. Effect of drain doping profile on double gate tunnel field effect transistor and its influence on device RF performance. IEEE Trans Nanotechnol, 2014, 13(5): 974 doi: 10.1109/TNANO.2014.2336812
[31]
ATLAS User's Manual, Silvaco Int. , Santa Clara, CA, April 20, 2010
[32]
Enz C C, Vittoz E A. Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. New York: Wiely, 2006

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    Received: 16 August 2016 Revised: 27 November 2016 Online: Published: 01 July 2017

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      Article Navigation >  Journal of Semiconductors  > 2017  >  38(7): 074003
      S.K. Vishvakarma, Ankur Beohar, Vikas Vijayvargiya, Priyal Trivedi. Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry[J]. Journal of Semiconductors, 2017, 38(7): 074003. doi: 10.1088/1674-4926/38/7/074003 S.K. Vishvakarma, A Beohar, V Vijayvargiya, P Trivedi. Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry[J]. J. Semicond., 2017, 38(7): 074003. doi: 10.1088/1674-4926/38/7/074003.Export: BibTex EndNote
      Citation:
      S.K. Vishvakarma, Ankur Beohar, Vikas Vijayvargiya, Priyal Trivedi. Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry[J]. Journal of Semiconductors, 2017, 38(7): 074003. doi: 10.1088/1674-4926/38/7/074003

      S.K. Vishvakarma, A Beohar, V Vijayvargiya, P Trivedi. Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry[J]. J. Semicond., 2017, 38(7): 074003. doi: 10.1088/1674-4926/38/7/074003.
      Export: BibTex EndNote
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      Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

      doi: 10.1088/1674-4926/38/7/074003

      • Discipline of Electrical Engineering, Indian Institute of Technology, Indore, 453446, India

      Funds:

      Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant No. 22/0651/14/EMR-Ⅱ, Government of India

      Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant 22/0651/14/EMR-Ⅱ, Government of India

      More Information
      • Corresponding author: S. K. Vishvakarma, Email: skvishvakarma@iiti.ac.in
      • Received Date: 2016-08-16
      • Revised Date: 2016-11-27
      • Published Date: 2017-07-01

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