SEMICONDUCTOR DEVICES

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

Mini Bhartia and Arun Kumar Chatterjee

+ Author Affiliations

 Corresponding author: Mini Bhartia, E-mail: er.minibhartia@gmail.com; Arun Kumar Chatterjee, E-mail: arun.chatterjee@thapar.edu

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Abstract: A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

Key words: double gate MOSFET2D potential distribution modeldrain current model



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Fig. 1.  A schematic diagram of the symmetric n-channel DG-MOSFET with structural definitions and a coordinate system.

Fig. 2.  Comparison between the simulated (symbol) and analytical modeled (solid lines) SS versus channel length.

Fig. 3.  The threshold voltage of undoped DG-MOSFETs at different silicon film thicknesses and channel lengths. The symbols are simulated values while the solid lines represent the analytical values.

Fig. 4.  Simulated (symbols) and model (solid lines) (a) output characteristic and (b) transfer characteristic representations in linear and semi-logarithmic forms for symmetrical DG-MOSFETs for $L =$ 32 nm, $t_{\rm si}$ $=$ 10 nm, $t_{\rm ox}$ $=$ 2 nm, $R_{\rm sd}$ $=$ 0 $\upOmega$.

Fig. 5.  Simulated (symbols) and model (solid lines) (a) output characteristic and (b) transfer characteristic representations in linear and semi-logarithmic forms for symmetrical DG-MOSFETs for $L =$ 45~nm, $t_{\rm si}$ $=$ 10 nm, $t_{\rm ox}$ $=$ 2 nm and $R_{\rm sd}$ $=$ 0 $\upOmega$.

Fig. 6.  Simulated (symbols) and model (solid lines) (a) output characteristic and (b) transfer characteristic representations in linear and semi-logarithmic forms for symmetrical DG-MOSFETs for $L$ $=$~32 nm, $t_{\rm si}$ $=$ 10 nm, $t_{\rm ox}$ $=$ 2 nm and $R_{\rm sd}$ $=$ 180 $\upOmega$.

Fig. 7.  Drain current variation simulated (symbol) and modeled (solid lines) with the oxide interface charge at different gate voltages.

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    Received: 15 September 2014 Revised: Online: Published: 01 April 2015

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      Mini Bhartia, Arun Kumar Chatterjee. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs[J]. Journal of Semiconductors, 2015, 36(4): 044003. doi: 10.1088/1674-4926/36/4/044003 M Bhartia, A K Chatterjee. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs[J]. J. Semicond., 2015, 36(4): 044003. doi:  10.1088/1674-4926/36/4/044003.Export: BibTex EndNote
      Citation:
      Mini Bhartia, Arun Kumar Chatterjee. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs[J]. Journal of Semiconductors, 2015, 36(4): 044003. doi: 10.1088/1674-4926/36/4/044003

      M Bhartia, A K Chatterjee. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs[J]. J. Semicond., 2015, 36(4): 044003. doi:  10.1088/1674-4926/36/4/044003.
      Export: BibTex EndNote

      Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

      doi: 10.1088/1674-4926/36/4/044003
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      • Corresponding author: E-mail: er.minibhartia@gmail.com; E-mail: arun.chatterjee@thapar.edu
      • Received Date: 2014-09-15
      • Accepted Date: 2014-11-24
      • Published Date: 2015-01-25

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