Fig. 1.
Block diagram of the cyclic ADC.
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Ye Han, Quanliang Li, Cong Shi, Nanjian Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016
Y Han, Q L Li, C Shi, N J Wu. A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors[J]. J. Semicond., 2013, 34(8): 085016. doi: 10.1088/1674-4926/34/8/085016.
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A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors
doi: 10.1088/1674-4926/34/8/085016
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Abstract
This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. -
References
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