SEMICONDUCTOR INTEGRATED CIRCUITS

A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors

Wei Liu, Tingcun Wei, Bo Li, Panjie Guo and Yongcai Hu

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 Corresponding author: Wei Liu, E-mail: liouwei930@sina.com

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Abstract: This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for multi-channel CdZnTe (CZT) detector applications. In order to improve the SAR-ADC's accuracy, a novel comparator is proposed in which the offset voltage is self-calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm2.

Key words: SARADCradiation-hardnesslow powerCZT detectors



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Fig. 1.  A block diagram of typical front-end electronics for multi-channel CZT detectors.

Fig. 2.  A typical architecture of a SAR-ADC.

Fig. 3.  The proposed SAR-ADC's frame.

Fig. 4.  The proposed comparator with offset voltage self-cancellation.

Fig. 5.  (a) The equivalent circuit for the offset voltage storage step. (b) The equivalent circuit for the signal amplifying step.

Fig. 6.  The architecture of the traditional capacitor-resistor hybrid SAR-ADC.

Fig. 7.  A comparison of the traditional and proposed charge scaling DACs. (a) Binary weighted capacitor array. (b) Unit capacitor array.

Fig. 8.  Major bit transition in a 4-bit SAR ADC with (a) a binary weighted capacitor array and (b) a unit capacitor array.

Fig. 9.  Noises isolation technologies.

Fig. 10.  Guard ring and distancing technologies.

Fig. 11.  SEL test results of the standard, 2 $\mu$-stretched and 5 $\mu$-stretched logic libraries. The cross-section of 10$^{-10}$ cm$^{-2}$ indicates that no latch-up events were observed at the points[18].

Fig. 12.  A chip photograph of the proposed SAR-ADC.

Fig. 13.  The nonlinearities of the proposed SAR ADC. (a) DNL. (b) INL.

Fig. 14.  The measured output spectrum ($f_{\rm in}$ $=$ 22.67 kHz, $f_{\rm s}$ $=$ 1~MS/s).

Table 1.   63 periodic DNL peaks appeared at $m$ $\times$ 2$^{6}$ ($m=$ 1, 2, $\cdots$, 63).

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Table 2.   Performance comparison.

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    Received: 23 September 2014 Revised: Online: Published: 01 April 2015

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      Wei Liu, Tingcun Wei, Bo Li, Panjie Guo, Yongcai Hu. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. Journal of Semiconductors, 2015, 36(4): 045007. doi: 10.1088/1674-4926/36/4/045007 W Liu, T C Wei, B Li, P J Guo, Y C Hu. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. J. Semicond., 2015, 36(4): 045007. doi: 10.1088/1674-4926/36/4/045007.Export: BibTex EndNote
      Citation:
      Wei Liu, Tingcun Wei, Bo Li, Panjie Guo, Yongcai Hu. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. Journal of Semiconductors, 2015, 36(4): 045007. doi: 10.1088/1674-4926/36/4/045007

      W Liu, T C Wei, B Li, P J Guo, Y C Hu. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. J. Semicond., 2015, 36(4): 045007. doi: 10.1088/1674-4926/36/4/045007.
      Export: BibTex EndNote

      A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors

      doi: 10.1088/1674-4926/36/4/045007
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      Project supported by the Special-Funded Program on National Key Scientific Instruments and Equipment Development (No. 2011YQ040082).

      More Information
      • Corresponding author: E-mail: liouwei930@sina.com
      • Received Date: 2014-09-23
      • Accepted Date: 2014-11-13
      • Published Date: 2015-01-25

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