| Citation: |
Shen Jinpeng, Wang Xin’an, Liu Shan, Zong Hongqiang, Huang Jinfeng, Yang Xin, Feng Xiaoxing, Ge Binjie. Design and implementation of an ultra-low power passive UHF RFID tag[J]. Journal of Semiconductors, 2012, 33(11): 115011. doi: 10.1088/1674-4926/33/11/115011
Shen J P, Wang X, Liu S, Zong H Q, Huang J F, Yang X, Feng X X, Ge B J. Design and implementation of an ultra-low power passive UHF RFID tag[J]. J. Semicond., 2012, 33(11): 115011. doi: 10.1088/1674-4926/33/11/115011.
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Design and implementation of an ultra-low power passive UHF RFID tag
doi: 10.1088/1674-4926/33/11/115011
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Abstract
This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm2. Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of -12 dBm.-
Keywords:
- UHF RFID tag,
- voltage reference,
- demodulator,
- low power
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] -
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