SEMICONDUCTOR INTEGRATED CIRCUITS

A 3 Gb/s multichannel transceiver in 65 nm CMOS technology

Feng Zhang1, and Yusong Qiu2

+ Author Affiliations

 Corresponding author: Feng Zhang, E-mail: Zhangfeng_ime@ime.ac.cn

PDF

Abstract: This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose rate is 3 Gb/s with a 5 pF load including the HBM 2000 V ESD protection. Equalizers and clock data recovery modules, CRC checkers and 8 b/10 b encoders are not added in the design for reducing the latency, and the whole latency is 7 ns without cables. Since the transceiver has many robust features including a process, voltage and temperature independent phase-locked loop with calibrations, the low skew differential clock tree, and a stable current mode driver with common mode feedback, the transceiver can work properly at different process corners and extreme temperatures, and also can tolerate 20% power supply variations. The transceiver can be applied for the interface of sub-100 nm high performance processors, which require low latency and high stability. The transceiver shows a bitter error ratio of less than 10-15 at 3 Gbps.

Key words: transceiverprocess variationlow latencyPLL



[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
Fig. 1.  16 bits transmitter architecture.

Fig. 2.  PLL architecture.

Fig. 3.  VCO circuit.

Fig. 4.  Calibration flow.

Fig. 5.  Process and temperature calibration for VCO.

Fig. 6.  VCO simulation results.

Fig. 7.  Small signal model of PLL.

Fig. 8.  VCO and reference clock noise contribution. (a) Open loop. (B) Close loop.

Fig. 9.  RC process calibrations.

Fig. 10.  Parallel receiver architecture.

Fig. 11.  Die photograph of the transceiver.

Fig. 12.  Phase of data line and clock line.

Fig. 13.  Clock transmitter jitter.

DownLoad: CSV

Table 1.   Comparison with other reported PLL.

DownLoad: CSV

Table 2.   The parallel transceiver performance summary.

DownLoad: CSV

Table 3.   Performance summary.

DownLoad: CSV
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2277 Times PDF downloads: 15 Times Cited by: 0 Times

    History

    Received: 28 June 2014 Revised: Online: Published: 01 January 2015

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Feng Zhang, Yusong Qiu. A 3 Gb/s multichannel transceiver in 65 nm CMOS technology[J]. Journal of Semiconductors, 2015, 36(1): 015003. doi: 10.1088/1674-4926/36/1/015003 F Zhang, Y S Qiu. A 3 Gb/s multichannel transceiver in 65 nm CMOS technology[J]. J. Semicond., 2015, 36(1): 015003. doi: 10.1088/1674-4926/36/1/015003.Export: BibTex EndNote
      Citation:
      Feng Zhang, Yusong Qiu. A 3 Gb/s multichannel transceiver in 65 nm CMOS technology[J]. Journal of Semiconductors, 2015, 36(1): 015003. doi: 10.1088/1674-4926/36/1/015003

      F Zhang, Y S Qiu. A 3 Gb/s multichannel transceiver in 65 nm CMOS technology[J]. J. Semicond., 2015, 36(1): 015003. doi: 10.1088/1674-4926/36/1/015003.
      Export: BibTex EndNote

      A 3 Gb/s multichannel transceiver in 65 nm CMOS technology

      doi: 10.1088/1674-4926/36/1/015003
      Funds:

      Project supported by the National High Technology Research and Development Program of China (No. 2011AA010403).

      More Information
      • Corresponding author: E-mail: Zhangfeng_ime@ime.ac.cn
      • Received Date: 2014-06-28
      • Accepted Date: 2014-08-18
      • Published Date: 2015-01-25

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return