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A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Bo Zhong and Zhangming Zhu

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 Corresponding author: Corresponding author. Email: zhongbo1127@163.com

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Abstract: A 0.1-1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal (MOM) capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.

Key words: phase lock loopfreqency synthesizerdual path charge pumpCMOS



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Fig1.  CP and LPF with dual paths. (a) Scheme. (b) Clock sequence and $V_{\rm vco}$ response.

Fig2.  (Color online) Phase noise of reference,CP and VCO in PLL output.

Fig3.  (a) PFD TSPC schematicand (b) dynamic current-matching CP.

Fig4.  Optimized phase noise spectrum of PFD and CP.

Fig5.  (a) Differential CMOS ring oscillator and (b) cell view of DINV.

Fig6.  The phase noise of VCO before/after optimization.

Fig7.  PLL die micro-photo.

Fig8.  Phase noise of output clock.

Fig9.  Lock time of PLL.

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Table 1.   The key parameters of single path and dual path CP PLL.

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Table 2.   Measured results.

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Table 3.   Summary of the PLL performance.

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    Received: 26 August 2015 Revised: Online: Published: 01 May 2016

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      Bo Zhong, Zhangming Zhu. A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process[J]. Journal of Semiconductors, 2016, 37(5): 055004. doi: 10.1088/1674-4926/37/5/055004 B Zhong, Z M Zhu. A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process[J]. J. Semicond., 2016, 37(5): 055004. doi: 10.1088/1674-4926/37/5/055004.Export: BibTex EndNote
      Citation:
      Bo Zhong, Zhangming Zhu. A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process[J]. Journal of Semiconductors, 2016, 37(5): 055004. doi: 10.1088/1674-4926/37/5/055004

      B Zhong, Z M Zhu. A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process[J]. J. Semicond., 2016, 37(5): 055004. doi: 10.1088/1674-4926/37/5/055004.
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      A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

      doi: 10.1088/1674-4926/37/5/055004
      Funds:

      Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the National High-Tech Program of China (No. 2013AA014103).

      More Information
      • Corresponding author: Corresponding author. Email: zhongbo1127@163.com
      • Received Date: 2015-08-26
      • Accepted Date: 2015-10-27
      • Published Date: 2016-01-25

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