SEMICONDUCTOR INTEGRATED CIRCUITS

A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques

Jiangzheng Cai, Suming Zhang, Jia Yuan, Xinchao Shang, Liming Chen and Yong Hei

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 Corresponding author: Jiangzheng Cai, Email: caijiangzheng@ime.ac.cn

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Abstract: This paper presents a 6 kb SRAM that uses a novel 10T cell to achieve a minimum operating voltage of 320 mV in a 130 nm CMOS process. A number of low power circuit techniques are included to enable the proposed SRAM to operate in the subthreshold region. The reverse short channel effect and the reverse narrow channel effect are utilized to improve the performance of the SRAM. A novel subthreshold pulse generation circuit produces an ideal pulse to make read operation stable. A floating write bit-line effectively reduces the standby leakage consumption. Finally, a short read bit-line makes the read operation fast and energy-saving. Measurements indicate that these techniques are effective, the SRAM can operate at 800 kHz and consume 1.94 μW at its lowest voltage (320 mV).

Key words: subthreshold SRAMlow power circuit techniquesreverse short channel effectreverse narrow channel effectsubthreshold pulsefloating write bit-line



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Fig. 1.  (Color online) (a) Proposed 10T SRAM cell. (b) Layout of the proposed 10T SRAM cell.

Fig. 2.  (a) RSCE effect. (b) RNCE effect.

Fig. 3.  The matched ratio of $W_{\rm p}$/$W_{\rm n}$ under TT and FNSP corner.

Fig. 4.  Implementation of the RSCE and the RNCE.

Fig. 5.  SNM of our SRAM cell and 6T cell.

Fig. 6.  Drivability of different widths of NMOS.

Fig. 7.  Traditional pulse generation circuit.

Fig. 8.  (Color online) Post simulation of inverter chain. (a) TT corner. (b) SNFP corner.

Fig. 9.  Novel pulse generation circuit.

Fig. 10.  (Color online) Post simulation of the novel pulse generation circuit. (a) 25 $\du$/SNFP. (b) -40 $\du$/SNFP.

Fig. 11.  Structure of our design.

Fig. 12.  0.3 V, SS corner, the read speed of different cells each bit-line.

Fig. 13.  The layout of the proposed SRAM.

Fig. 14.  Test power curve of the SRAM.

Fig. 15.  Function of the SRAM at 320 mV.

Table 1.   Comparison of fall and rise time of different cells each bit-line.

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Table 2.   Comparison of the proposed SRAM and conventional 6T SRAM.

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Table 3.   Comparison of the proposed SRAM and other subthreshold SRAMs.

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    Received: 06 November 2014 Revised: Online: Published: 01 June 2015

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      Jiangzheng Cai, Suming Zhang, Jia Yuan, Xinchao Shang, Liming Chen, Yong Hei. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques[J]. Journal of Semiconductors, 2015, 36(6): 065007. doi: 10.1088/1674-4926/36/6/065007 J Z Cai, S M Zhang, J Yuan, X C Shang, L M Chen, Y Hei. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques[J]. J. Semicond., 2015, 36(6): 065007. doi: 10.1088/1674-4926/36/6/065007.Export: BibTex EndNote
      Citation:
      Jiangzheng Cai, Suming Zhang, Jia Yuan, Xinchao Shang, Liming Chen, Yong Hei. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques[J]. Journal of Semiconductors, 2015, 36(6): 065007. doi: 10.1088/1674-4926/36/6/065007

      J Z Cai, S M Zhang, J Yuan, X C Shang, L M Chen, Y Hei. A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques[J]. J. Semicond., 2015, 36(6): 065007. doi: 10.1088/1674-4926/36/6/065007.
      Export: BibTex EndNote

      A 320 mV, 6 kb subthreshold 10T SRAM employing voltage lowering techniques

      doi: 10.1088/1674-4926/36/6/065007
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      Project supported by the National Natural Science Foundation of China (No. 61306039) and the Next Generation of Information Technology for Sensing China (No. XDA06020401).

      More Information
      • Corresponding author: Email: caijiangzheng@ime.ac.cn
      • Received Date: 2014-11-06
      • Accepted Date: 2014-12-05
      • Published Date: 2015-01-25

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