| Citation: |
Liu Yongwang, Wang Zhigong, Li Wei. 2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit[J]. Journal of Semiconductors, 2007, In Press.
Liu Y W, Wang Z G, Li W. 2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit[J]. Chin. J. Semicond., 2007, 28(5): 692.
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2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit
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Abstract
A 2.5Gb/s/ch data recovery (DR) circuit is designed for an SFI-5 interface.To make the parallel data bit-synchronization and reduce the bit error rate (BER),a delay locked loop (DLL) is used to place the center of the data eye exactly at the rising edge of the data-sampling clock.A single channel DR circuit was fabricated in TSMC’s standard 0.18μm CMOS process.The chip area is 0.46mm2.With a 231-1 pseudorandom bit sequence (PRBS) input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps.The sensitivity of the single channel DR is less than 20mV with 1e12 BER.-
Keywords:
- data recovery,
- delay locked loop,
- bit-synchronization
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References
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Proportional views
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