| Citation: |
Bai Na, Lü Baitao. A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process[J]. Journal of Semiconductors, 2012, 33(6): 065008. doi: 10.1088/1674-4926/33/6/065008
Bai N, Lü B T. A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process[J]. J. Semicond., 2012, 33(6): 065008. doi: 10.1088/1674-4926/33/6/065008.
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A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process
doi: 10.1088/1674-4926/33/6/065008
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Abstract
A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage (200 mV) applications. Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes. To minimize leakage, a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty. Combined with buffering circuit and reconfigurable operation, the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region. Compared to the referenced subthreshold SRAM bitcell, the proposed bitcell shows: (1) a better critical state noise margin, and (2) smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13 μW power consumption at 138 kHz frequency.-
Keywords:
- subthreshold SRAM,
- static noise margin,
- leakage,
- ultra low power
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References
[1] [2] [3] [4] [5] [6] [7] [8] -
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