Chin. J. Semicond. > 2005, Volume 26 > Issue 11 > 2062-2068

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Abstract: This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes.The method makes a full analysis of the factors which influence test parameters:compression ratio,test application time,and area overhead.To improve the compression ratio,the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step.With a novel on-chip decoder,low test application time and low area overhead are obtained by hybrid run length codes.Finally,an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method.

Key words: test data compressionunspecified bits assignmentsystem-on-a-chip testhybrid run-length codes

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    Received: 19 August 2015 Revised: Online: Published: 01 November 2005

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      Fang Jianping, Hao Yue, Liu Hongxia, Li Kang. An Efficient Test Data Compression Technique Based on Codes[J]. Journal of Semiconductors, 2005, In Press. Fang J P, Hao Y, Liu H X, Li K. An Efficient Test Data Compression Technique Based on Codes[J]. Chin. J. Semicond., 2005, 26(11): 2062.Export: BibTex EndNote
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      Fang Jianping, Hao Yue, Liu Hongxia, Li Kang. An Efficient Test Data Compression Technique Based on Codes[J]. Journal of Semiconductors, 2005, In Press.

      Fang J P, Hao Y, Liu H X, Li K. An Efficient Test Data Compression Technique Based on Codes[J]. Chin. J. Semicond., 2005, 26(11): 2062.
      Export: BibTex EndNote

      An Efficient Test Data Compression Technique Based on Codes

      • Received Date: 2015-08-19

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