SEMICONDUCTOR DEVICES

An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

Ye Fan, Xiaorong Luo, Kun Zhou, Yuanhang Fan, Yongheng Jiang, Qi Wang, Pei Wang, Yinchun Luo and Bo Zhang

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 Corresponding author: Luo Xiaorong, Email: xrluo@uestc.edu.cn

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Abstract: A low specific on-resistance (Ron, sp) SOI NBL TLDMOS (silicon-on-insulator trench LDMOS with an N buried layer) is proposed. It has three features:a thin N buried layer (NBL) on the interface of the SOI layer/buried oxide (BOX) layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer. First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the Ron, sp. Second, in the y-direction, the BOX's electric field (E-field) strength is increased to 154 V/μm from 48 V/μm of the SOI Trench Gate LDMOS (SOI TG LDMOS) owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage (BV), but also reduces the cell pitch and Ron, sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 μm, and decreases the Ron, sp by 80% at the same BV.

Key words: MOSFETsilicon-on-insulatorbreakdown voltagespecific on-resistance



[1]
Colak S, Singer B, Stupp E. Lateral DMOS power transistor design. IEEE Electron Device Lett, 1980, 1(4):51 doi: 10.1109/EDL.1980.25226
[2]
Hossain Z, Imam M, Fulton J, et al. Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance. IEEE ISPSD, 2002:137 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1016190&pageNumber%3D33887%26rowsPerPage%3D100
[3]
Zhou M J, De Bruycker A, Van Calster A, et al. Breakdown walkout and its reduction in high-voltage pLDMOS transistors on thin epitaxial layer. Electron Lett, 1992, 28(16):1537 doi: 10.1049/el:19920976
[4]
Efland T, Mei P, Mosher D, et al. Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent Rsp vs BV performance. IEEE ISPSD, 1996:147 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=509468
[5]
Lei Tianfei, Luo Xiaorong, Ge Rui, et al. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET. Journal of Semiconductors, 2011, 32(10):104004 doi: 10.1088/1674-4926/32/10/104004
[6]
Hu Xiarong, Zhang Bo, Luo Xiaorong, et al. Universal trench design method for a high-voltage SOI trench LDMOS. Journal of Semiconductors, 2012, 33(7):074006 doi: 10.1088/1674-4926/33/7/074006
[7]
Son W S, Sohn Y H, Choi S Y. RESURF LDMOSFET with a trench for SOI power integrated circuits. Microelectron J, 2004, 35(5):393 doi: 10.1016/j.mejo.2004.02.001
[8]
Nakagawa A, Kawaguchi Y. Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 mΩ·mm2. IEEE ISPSD, 2000:47 https://ar.scribd.com/document/342904311/PowerManagement-SamDavis
[9]
Luo X R, Li Z J, Zhang B, et al. Realization of high voltage (>> 700 V) in new soi devices with a compound buried layer. IEEE Electron Device Lett, 2008, 29(12):1395 doi: 10.1109/LED.2008.2007307
[10]
Chen M, Wang Y B. Overview of SOI technologies in China. IEEE International SOI Conference, 2009:1 http://ieeexplore.ieee.org/abstract/document/5318787
[11]
Hu S D, Zhang B, Li Z J, et al. A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device. Chin Phys B, 2010, 19(3):37303 doi: 10.1088/1674-1056/19/3/037303
[12]
Luo Xiaorong, Hu Gangyi, Zhou Kun, et al. High voltage SOI LDMOS with a compound buried layer. Journal of Semiconductors, 2012, 33(10):104003 doi: 10.1088/1674-4926/33/10/104003
[13]
Nakagawa A, Yasuhara N, Baba Y. Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film. IEEE Trans Electron Devices, 1991, 38(7):1650 doi: 10.1109/16.85162
[14]
Luo X R, Wang Y G, Yao G L, et al. Partial SOI power LDMOS with a variable low-k dielectric buried layer and a buried p-layer. IEEE ICSICT, 2010:2061 http://cpb.iphy.ac.cn/EN/article/downloadArticleFile.do?attachType=PDF&id=25242
[15]
Yang X M, Zhang B, Luo X R. Double enhance dielectric layer electric field high voltage SOI LDMOS. IEEE EDSSC, 2011:1 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6117731
[16]
Yan T, Liao H, Xiong Y, et al. Cost-effective integrated RF power transistor in 0.18-μm CMOS technology. IEEE Electron Device Lett, 2006, 27(10):856 doi: 10.1109/LED.2006.882568
[17]
Yasuhara N, Nakagawa A, Furukawa K. SOI device structures implementing 650 V high voltage output devices on VLSIs. Electron Devices Meeting, 1991:141 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=235481
Fig. 1.  Schematic cross sections of (a) the proposed SOI NBL TLDMOS, (b) the charges distribution and the E-field profiles along the CC' line, (c) SOI TLDMOS, and (d) SOI TG LDMOS.

Fig. 2.  E-field distribution in the $y$-direction under the drain ($t_{\rm s}$ $=$ 4 $\mu $m, $t_{\rm I}$ $=$ 0.5 $\mu $m, $D_{\rm T}$ $=$ 3 $\mu $m, $W_{\rm T}$ $=$ 3 $\mu $m, $t_{\rm NBL}$ $=$ 0.5 $\mu $m, and a cell pitch of 6 $\mu $m); $N_{\rm D}$ and $N_{\rm NBL}$ are optimized for each device.

Fig. 3.  E-field distributions in the (a) $x$-direction ($y=0$), (b) around the oxide trench ($t_{\rm s}$ $=$ 4 $\mu $m, $t_{\rm I}$ $=$ 0.5 $\mu $m, $D_{\rm T}$ $=$ 3 $\mu$m, $W_{\rm T}$ $=$ 3 $\mu $m, $t_{\rm NBL}$ $=$ 0.5 $\mu $m, and a cell pitch of 6 $\mu $m); $N_{\rm D}$ and $N_{\rm NBL}$ are optimized to obtain the maximum BV for each device.

Fig. 4.  Equi-potential contours at breakdown for (a) SOI NBL TLDMOS (166 V), (b) SOI TLDMOS (143 V), (c) SOI TG LDMOS (81 V) (10 V/contour, $t_{\rm s}$ $=$ 4 $\mu $m, $t_{\rm I}$ $=$ 0.5 $\mu $m).

Fig. 5.  Current flowline contours for (a) SOI NBL TLDMOS, (b) SOI TLDMOS, and (c) SOI TG LDMOS (1.5 $\times $ 10$^{-6}$ A$\cdot$$\mu $m$^{-1}$/contour, $t_{\rm s}$ $=$ 4 $\mu $m, $t_{\rm I}$ $=$ 0.5 $\mu $m).

Fig. 6.  Dependencies of BV and $R_{\rm on, \, sp}$ on $t_{\rm NBL}$ and $N_{\rm NBL}$ for SOI NBL TLDMOS. (a) $t_{\rm NBL}$($N_{\rm NBL}$ $=$ 4.5 $\times$ 10$^{16}$ cm$^{-3}$). (b) $N_{\rm NBL }$($t_{\rm NBL}$ $=$ 0.5 $\mu $m). $N_{\rm D}$ is optimized for each $t_{\rm NBL}$ and $N_{\rm NBL}$. $D_{\rm T}$ $=$ 3 $\mu$m, $W_{\rm T}$ $=$ 3 $\mu$m, $t_{\rm s}$ $=$ 4 $\mu$m, $t_{\rm I}$ $=$ 0.5 $\mu$m, and cell pitch of 6 $\mu$m for (a) and (b).

Fig. 7.  Dependencies of BV and $R_{\rm on, \, sp}$ on $N_{\rm D}$, $D_{\rm T}$ and $W_{\rm T}$ for SOI NBL TLDMOS. (a) $N_{\rm D}$ ($W_{\rm T}$ $=$ 3 $\mu $m). (b) $D_{\rm T}$ ($W_{\rm T}$ $=$ 3 $\mu $m). (c) $W_{\rm T}$ ($D_{\rm T}$ $=$ 3 $\mu $m). $t_{\rm s}$ $=$ 4 $\mu $m, $t_{\rm I}$ $=$ 0.5 $\mu $m, $t_{\rm NBL}$ $=$ 0.5 $\mu $m and $N_{\rm NBL}$ $=$ 4.5 $\times $ 10$^{16}$ cm$^{-3}$.

Fig. 8.  Key process steps to fabricate a prototype SOI NBL TLDMOS. (a) Form the NBL and bonding. (b) Preoxidation, etch Si to form the oxide trench. (c) Form the p-well, p$^{+}$ contact and n$^{+}$ source/drain regions. (d) Deposit ploy-silicon to form the trench gate and finally form the electrodes.

Table 1.   Optimized NNBL, ND, BV and Ron; sp for SOI NBL TLDMOS, TLDMOS and TG LDMOS.

[1]
Colak S, Singer B, Stupp E. Lateral DMOS power transistor design. IEEE Electron Device Lett, 1980, 1(4):51 doi: 10.1109/EDL.1980.25226
[2]
Hossain Z, Imam M, Fulton J, et al. Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance. IEEE ISPSD, 2002:137 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1016190&pageNumber%3D33887%26rowsPerPage%3D100
[3]
Zhou M J, De Bruycker A, Van Calster A, et al. Breakdown walkout and its reduction in high-voltage pLDMOS transistors on thin epitaxial layer. Electron Lett, 1992, 28(16):1537 doi: 10.1049/el:19920976
[4]
Efland T, Mei P, Mosher D, et al. Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent Rsp vs BV performance. IEEE ISPSD, 1996:147 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=509468
[5]
Lei Tianfei, Luo Xiaorong, Ge Rui, et al. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET. Journal of Semiconductors, 2011, 32(10):104004 doi: 10.1088/1674-4926/32/10/104004
[6]
Hu Xiarong, Zhang Bo, Luo Xiaorong, et al. Universal trench design method for a high-voltage SOI trench LDMOS. Journal of Semiconductors, 2012, 33(7):074006 doi: 10.1088/1674-4926/33/7/074006
[7]
Son W S, Sohn Y H, Choi S Y. RESURF LDMOSFET with a trench for SOI power integrated circuits. Microelectron J, 2004, 35(5):393 doi: 10.1016/j.mejo.2004.02.001
[8]
Nakagawa A, Kawaguchi Y. Improved 20 V lateral trench gate power MOSFETs with very low on-resistance of 7.8 mΩ·mm2. IEEE ISPSD, 2000:47 https://ar.scribd.com/document/342904311/PowerManagement-SamDavis
[9]
Luo X R, Li Z J, Zhang B, et al. Realization of high voltage (>> 700 V) in new soi devices with a compound buried layer. IEEE Electron Device Lett, 2008, 29(12):1395 doi: 10.1109/LED.2008.2007307
[10]
Chen M, Wang Y B. Overview of SOI technologies in China. IEEE International SOI Conference, 2009:1 http://ieeexplore.ieee.org/abstract/document/5318787
[11]
Hu S D, Zhang B, Li Z J, et al. A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device. Chin Phys B, 2010, 19(3):37303 doi: 10.1088/1674-1056/19/3/037303
[12]
Luo Xiaorong, Hu Gangyi, Zhou Kun, et al. High voltage SOI LDMOS with a compound buried layer. Journal of Semiconductors, 2012, 33(10):104003 doi: 10.1088/1674-4926/33/10/104003
[13]
Nakagawa A, Yasuhara N, Baba Y. Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film. IEEE Trans Electron Devices, 1991, 38(7):1650 doi: 10.1109/16.85162
[14]
Luo X R, Wang Y G, Yao G L, et al. Partial SOI power LDMOS with a variable low-k dielectric buried layer and a buried p-layer. IEEE ICSICT, 2010:2061 http://cpb.iphy.ac.cn/EN/article/downloadArticleFile.do?attachType=PDF&id=25242
[15]
Yang X M, Zhang B, Luo X R. Double enhance dielectric layer electric field high voltage SOI LDMOS. IEEE EDSSC, 2011:1 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6117731
[16]
Yan T, Liao H, Xiong Y, et al. Cost-effective integrated RF power transistor in 0.18-μm CMOS technology. IEEE Electron Device Lett, 2006, 27(10):856 doi: 10.1109/LED.2006.882568
[17]
Yasuhara N, Nakagawa A, Furukawa K. SOI device structures implementing 650 V high voltage output devices on VLSIs. Electron Devices Meeting, 1991:141 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=235481
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    Received: 01 August 2013 Revised: 12 September 2013 Online: Published: 01 March 2014

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      Ye Fan, Xiaorong Luo, Kun Zhou, Yuanhang Fan, Yongheng Jiang, Qi Wang, Pei Wang, Yinchun Luo, Bo Zhang. An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement[J]. Journal of Semiconductors, 2014, 35(3): 034011. doi: 10.1088/1674-4926/35/3/034011 Y Fan, X R Luo, K Zhou, Y H Fan, Y H Jiang, Q Wang, P Wang, Y C Luo, B Zhang. An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement[J]. J. Semicond., 2014, 35(3): 034011. doi: 10.1088/1674-4926/35/3/034011.Export: BibTex EndNote
      Citation:
      Ye Fan, Xiaorong Luo, Kun Zhou, Yuanhang Fan, Yongheng Jiang, Qi Wang, Pei Wang, Yinchun Luo, Bo Zhang. An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement[J]. Journal of Semiconductors, 2014, 35(3): 034011. doi: 10.1088/1674-4926/35/3/034011

      Y Fan, X R Luo, K Zhou, Y H Fan, Y H Jiang, Q Wang, P Wang, Y C Luo, B Zhang. An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement[J]. J. Semicond., 2014, 35(3): 034011. doi: 10.1088/1674-4926/35/3/034011.
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      An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement

      doi: 10.1088/1674-4926/35/3/034011
      Funds:

      Project supported by the National Natural Science Foundation of China (No. 61176069), the Program for New Century Excellent Talents in University of Ministry of Education of China (No. NCET-11-0062), and the China Postdoctoral Science Foundation (No. 2012T50771)

      the China Postdoctoral Science Foundation 2012T50771

      the National Natural Science Foundation of China 61176069

      the Program for New Century Excellent Talents in University of Ministry of Education of China NCET-11-0062

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      • Corresponding author: Luo Xiaorong, Email: xrluo@uestc.edu.cn
      • Received Date: 2013-08-01
      • Revised Date: 2013-09-12
      • Published Date: 2014-03-01

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