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A novel compact model for on-chip stacked transformers in RF-CMOS technology

Jun Liu, Jincai Wen, Qian Zhao and Lingling Sun

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 Corresponding author: Liu Jun, Email:ljun77@163.com

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Abstract: A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1:1 stacked transformer manufactured in a commercial RF-CMOS technology.

Key words: on-chipstacked transformercompact model



[1]
Zolfaghari A, Chan A, Razavi B. Stacked inductors and transformers in CMOS technology. IEEE J Solid-State Circuits, 200136(4):620 doi: 10.1109/4.913740
[2]
Cen C, Lin Y, Chen C, et al. High-coupling and ultra-low-loss interlaced stacked transformers for 60-100 GHz CMOS RFIC applications. IEEE Radio and Wireless Symposium, 2007:357 http://ieeexplore.ieee.org/document/4160725/?reload=true&arnumber=4160725&contentType=Conference%20Publications
[3]
Fong N, Plouchart J O, Zamdmer N, et al. High-performance and area-efficient stacked transformers for RF CMOS integrated circuits. IEEE MTT-S International Microwave Symposium, 2003, 2:967 http://ieeexplore.ieee.org/document/1212530/?arnumber=1212530
[4]
Gao W, Jiao C, Liu T, et al. Scalable compact circuit model for differential spiral transformers in CMOS RFICs. IEEE Trans Electron Devices, 2006, 53(9):2187 doi: 10.1109/TED.2006.880230
[5]
Lim C C, Yeo K S, Chew K W, et al. Fully symmetrical monolithic transformer (true 1:1) for silicon RFIC. IEEE Trans Microw Theory Tech, 2008, 56(10):2301 doi: 10.1109/TMTT.2008.2003531
[6]
Biondi T, Scuderi A, Ragonese E, et al. Analysis and modeling of layout scaling in silicon integrated stacked transformers. IEEE Trans Microw Theory Tech, 2006, 54(5):2203 doi: 10.1109/TMTT.2006.872788
[7]
Mayevskiy Y, Watson A, Francis P, et al. A new compact model for monolithic transformers in silicon-based RFICs. IEEE Microw Wireless Compon Lett, 2005, 15(6):419 doi: 10.1109/LMWC.2005.850558
[8]
Chuan W, Liao H, Yongzhong X, et al. A physics-based equivalent-circuit model for on-chip symmetric transformers with accurate substrate modeling. IEEE Trans Microw Theory Tech, 2009, 57(4):980 doi: 10.1109/TMTT.2009.2014479
[9]
Arcioni P, Castello R, Perregrini L, et al. An innovative modelization of loss mechanism in silicon integrated inductors. IEEE Trans Circuits Syst Ⅱ, 1999, 46(12):1453 doi: 10.1109/82.809531
[10]
Chuan W, Liao H, Li C, et al. A wideband predictive double-π equivalent-circuit model for on-chip spiral inductors. IEEE Trans Electron Devices, 2009, 56(4):609 doi: 10.1109/TED.2009.2014184
[11]
Jun L, Lin Z, Huang W, et al. Double-fully scalable model for on-chip spiral inductors. Journal of Semiconductors, 2012, 33(8):084007 doi: 10.1088/1674-4926/33/8/084007
Fig. 1.  Simplified layout plane of a 1 : 1 on-chip stacked transformer. $d_{\rm in}$ and $d_{\rm out}$ are the inner and outer diameters of primary and secondary coils, respectively. $w$ is the width of metal coils. $L_{\rm gap}$ represent the gap distance from the port 1/2 (P1/2) to port 3/4 (P3/4). The sixth (top) metal M6 and fifth metal M5 were employed for the primary and secondary coils, respectively, whereas the first metal layer M6 was used for both the underpass and ground plane.

Fig. 2.  Topology of the proposed model. $C_{\rm t1}$ and $C_{\rm t2}$ are the turn-turn capacitor of the primary and secondary coil, respectively. $L_{i0}$ and $R_{i0}$ ($i$ $=$ 1, 2, 3) are the DC inductors and resistors of the primary and secondary coil, respectively. $L_{i1}$ and $R_{i1}$ ($i$ $=$ 1, 2, 3) represent the skin and proximity effect caused inductive and resistive parasitics of the primary and secondary coil, respectively. $C_{\rm p1}$ and $C_{\rm p2}$ represent the capacitors between the primary and secondary coil, respectively. $C_{{\rm ox}i}$ ($i$ $=$ 1, 2) in blocks D, E and F is the oxide capacitor, while $R_{{\rm sub}i}$ and $C_{{\rm sub}i}$ ($i$ $=$ 1, 2) are employed to characterize the losses caused by silicon substrate. The elements $C_{\rm ox3}$ and $R_{\rm sub3}$ in block F are introduced to capture the non-ideal parasitics between the primary coil and substrate. The $k_0$ and $k_1$ are the coupling coefficients between the primary and secondary coil. The coefficients $k_2$, $k_3$ and the elements $L_{\rm e}$ and $R_{\rm e}$ are used to characterize the substrate eddy current effect of the primary and secondary coil, respectively. The $L_{\rm e}$ and $R_{\rm e}$ are calculated using the method proposed in Ref. [10].

Fig. 3.  Simplified equivalent circuit for 1 : 1 stacked transformer model parameter extraction in two-port measurement. $C_{\rm t1}$ and $C_{\rm t2}$ are canceled. $Z_{\rm A}$, $Z_{\rm B}$, $Z_{\rm C}$, and $Z_{\rm E}$ are the $Z$-parameters of blocks A, B C and E, respectively. $Z_{\rm R}$ is the reflected impedance from P2 to P1, where $M =$ $k_0(L_{10}L_{30})^{1/2}, $ $Z_{\rm cp}$ $=$ 1/j$\omega C_{\rm p2}$.

Fig. 4.  Extracted $C_{\rm ox3}$ and $R_{\rm sub3}$ versus frequency characteristics. The average values at the range from 10 to 20 GHz are used in this work. The value of $R_{\rm sub3}$ calculated from Eq. (9) is also plotted: the value is close to 1500 $\Omega $.

Fig. 5.  Comparison of the model simulated and measured inductance of $P_1$ ($L_{11}$), $P_2$ ($L_{22}$) and the MAG characteristics.

Fig. 6.  Comparison of the model simulated and measured $S$-parameters.

Table 1.   Values of the model elements of the 1 : 1 stacked transformer.

[1]
Zolfaghari A, Chan A, Razavi B. Stacked inductors and transformers in CMOS technology. IEEE J Solid-State Circuits, 200136(4):620 doi: 10.1109/4.913740
[2]
Cen C, Lin Y, Chen C, et al. High-coupling and ultra-low-loss interlaced stacked transformers for 60-100 GHz CMOS RFIC applications. IEEE Radio and Wireless Symposium, 2007:357 http://ieeexplore.ieee.org/document/4160725/?reload=true&arnumber=4160725&contentType=Conference%20Publications
[3]
Fong N, Plouchart J O, Zamdmer N, et al. High-performance and area-efficient stacked transformers for RF CMOS integrated circuits. IEEE MTT-S International Microwave Symposium, 2003, 2:967 http://ieeexplore.ieee.org/document/1212530/?arnumber=1212530
[4]
Gao W, Jiao C, Liu T, et al. Scalable compact circuit model for differential spiral transformers in CMOS RFICs. IEEE Trans Electron Devices, 2006, 53(9):2187 doi: 10.1109/TED.2006.880230
[5]
Lim C C, Yeo K S, Chew K W, et al. Fully symmetrical monolithic transformer (true 1:1) for silicon RFIC. IEEE Trans Microw Theory Tech, 2008, 56(10):2301 doi: 10.1109/TMTT.2008.2003531
[6]
Biondi T, Scuderi A, Ragonese E, et al. Analysis and modeling of layout scaling in silicon integrated stacked transformers. IEEE Trans Microw Theory Tech, 2006, 54(5):2203 doi: 10.1109/TMTT.2006.872788
[7]
Mayevskiy Y, Watson A, Francis P, et al. A new compact model for monolithic transformers in silicon-based RFICs. IEEE Microw Wireless Compon Lett, 2005, 15(6):419 doi: 10.1109/LMWC.2005.850558
[8]
Chuan W, Liao H, Yongzhong X, et al. A physics-based equivalent-circuit model for on-chip symmetric transformers with accurate substrate modeling. IEEE Trans Microw Theory Tech, 2009, 57(4):980 doi: 10.1109/TMTT.2009.2014479
[9]
Arcioni P, Castello R, Perregrini L, et al. An innovative modelization of loss mechanism in silicon integrated inductors. IEEE Trans Circuits Syst Ⅱ, 1999, 46(12):1453 doi: 10.1109/82.809531
[10]
Chuan W, Liao H, Li C, et al. A wideband predictive double-π equivalent-circuit model for on-chip spiral inductors. IEEE Trans Electron Devices, 2009, 56(4):609 doi: 10.1109/TED.2009.2014184
[11]
Jun L, Lin Z, Huang W, et al. Double-fully scalable model for on-chip spiral inductors. Journal of Semiconductors, 2012, 33(8):084007 doi: 10.1088/1674-4926/33/8/084007
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    Received: 13 March 2013 Revised: 02 May 2013 Online: Published: 01 August 2013

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      Jun Liu, Jincai Wen, Qian Zhao, Lingling Sun. A novel compact model for on-chip stacked transformers in RF-CMOS technology[J]. Journal of Semiconductors, 2013, 34(8): 084006. doi: 10.1088/1674-4926/34/8/084006 J Liu, J C Wen, Q Zhao, L L Sun. A novel compact model for on-chip stacked transformers in RF-CMOS technology[J]. J. Semicond., 2013, 34(8): 084006. doi: 10.1088/1674-4926/34/8/084006.Export: BibTex EndNote
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      Jun Liu, Jincai Wen, Qian Zhao, Lingling Sun. A novel compact model for on-chip stacked transformers in RF-CMOS technology[J]. Journal of Semiconductors, 2013, 34(8): 084006. doi: 10.1088/1674-4926/34/8/084006

      J Liu, J C Wen, Q Zhao, L L Sun. A novel compact model for on-chip stacked transformers in RF-CMOS technology[J]. J. Semicond., 2013, 34(8): 084006. doi: 10.1088/1674-4926/34/8/084006.
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      A novel compact model for on-chip stacked transformers in RF-CMOS technology

      doi: 10.1088/1674-4926/34/8/084006
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      • Corresponding author: Liu Jun, Email:ljun77@163.com
      • Received Date: 2013-03-13
      • Revised Date: 2013-05-02
      • Published Date: 2013-08-01

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