Fig. 1.
Basic schematic of the CMOS inverter consisting of a parasitic p-n-p-n structure.
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Xinhai Yu, Changchun Chai, Xingrong Ren, Yintang Yang, Xiaowen Xi, Yang Liu. Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave[J]. Journal of Semiconductors, 2014, 35(8): 084011. doi: 10.1088/1674-4926/35/8/084011
X H Yu, C C Chai, X R Ren, Y T Yang, X W Xi, Y Liu. Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave[J]. J. Semicond., 2014, 35(8): 084011. doi: 10.1088/1674-4926/35/8/084011.
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Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave
doi: 10.1088/1674-4926/35/8/084011
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Abstract
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P=ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value. -
References
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