SEMICONDUCTOR DEVICES

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

Xiaorong Luo1, 2, , Xiaowei Wang2, Gangyi Hu1, Yuanhang Fan2, Kun Zhou2, Yinchun Luo2, Ye Fan2, Zhengyuan Zhang1, Yong Mei1 and Bo Zhang2

+ Author Affiliations

 Corresponding author: Luo Xiaorong, xrluo@uestc.edu.cn

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Abstract: An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (εox) than that of Si (εSi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

Key words: MOSFETSOIbreakdown voltagetrench gate



[1]
Sona W S, Sohnb Y H, Choia S Y. RESURF LDMOSFET with a trench for SOI power integrated circuits. Microelectron J, 2004, 35(5):393 doi: 10.1016/j.mejo.2004.02.001
[2]
Fujishima N, Andre C, Salama T. A trench lateral power MOSFET using self-aligned trench bottom contact holes. IEDM Tech Dig, 1997:359 http://ieeexplore.ieee.org/document/650399/authors
[3]
Fujishima N, Sugi A, Andre C, et al. Method of manufacturing a semiconductor integrated circuit device. US Patent, No.7445983, 2008
[4]
Fujishima N, Sugi A, Andre C, et al. Trench-type MOSFET having a reduced device pitch and on-resistance. US Patent, No.7005352B2, 2006
[5]
Varadarajan K R, Chow T P, Wang J. 250 V integrable silicon lateral trench power MOSFETs with superior specific on-resistance. Proc ISPSD, 2007:233 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4294975
[6]
Luo X, Zhang B, Li Z J. A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer. Solid State Electron, 2007, 51(3):493 doi: 10.1016/j.sse.2007.01.034
[7]
Luo X, Li Z J, Zhang B, et al. Realization of high voltage (≫700 V) in new SOI devices with a compound buried-layer. IEEE Electron Device Lett, 2008, 29(12):1395 doi: 10.1109/LED.2008.2007307
[8]
Luo X, Zhang B, Li Z J. A novel 700-V SOI LDMOS with double-sided trench. IEEE Electron Device Lett, 2007, 28(5):422 doi: 10.1109/LED.2007.894648
Fig. 1.  (a) Schematic cross-section and (b) layout design of the SOI DTMOS.

Fig. 2.  Electric field distributions in the (a) y-direction (x = 9.4 µm), (b) x-direction (y = 3 µm), and (c) around the oxide trench (tS =5 µm, tI = 1 µm for all, WT = DT = 3 µm for DTMOS).

Fig. 3.  Equipotent contours (10 V/contour) at breakdown (with thesame parameters as those of Fig. 2) (a) DTMOS (187 V), (b) TGMOS(80 V), and (c) C-LDMOS (84 V).

Fig. 4.  Influences of Nd and DT on BV for three MOSFETs (WT =3 µm).

Fig. 5.  Key process steps of the DTMOS.

Fig. 6.  Experimental results (a) micrographs of IC with parallel DTMOS devices and (b) off-state and (c) on-state IV measured curves (tS =5 µm, tI = 1 µm, WT = DT = 3 µm).

[1]
Sona W S, Sohnb Y H, Choia S Y. RESURF LDMOSFET with a trench for SOI power integrated circuits. Microelectron J, 2004, 35(5):393 doi: 10.1016/j.mejo.2004.02.001
[2]
Fujishima N, Andre C, Salama T. A trench lateral power MOSFET using self-aligned trench bottom contact holes. IEDM Tech Dig, 1997:359 http://ieeexplore.ieee.org/document/650399/authors
[3]
Fujishima N, Sugi A, Andre C, et al. Method of manufacturing a semiconductor integrated circuit device. US Patent, No.7445983, 2008
[4]
Fujishima N, Sugi A, Andre C, et al. Trench-type MOSFET having a reduced device pitch and on-resistance. US Patent, No.7005352B2, 2006
[5]
Varadarajan K R, Chow T P, Wang J. 250 V integrable silicon lateral trench power MOSFETs with superior specific on-resistance. Proc ISPSD, 2007:233 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4294975
[6]
Luo X, Zhang B, Li Z J. A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer. Solid State Electron, 2007, 51(3):493 doi: 10.1016/j.sse.2007.01.034
[7]
Luo X, Li Z J, Zhang B, et al. Realization of high voltage (≫700 V) in new SOI devices with a compound buried-layer. IEEE Electron Device Lett, 2008, 29(12):1395 doi: 10.1109/LED.2008.2007307
[8]
Luo X, Zhang B, Li Z J. A novel 700-V SOI LDMOS with double-sided trench. IEEE Electron Device Lett, 2007, 28(5):422 doi: 10.1109/LED.2007.894648
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    Received: 12 July 2013 Revised: 07 August 2013 Online: Published: 01 February 2014

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      Xiaorong Luo, Xiaowei Wang, Gangyi Hu, Yuanhang Fan, Kun Zhou, Yinchun Luo, Ye Fan, Zhengyuan Zhang, Yong Mei, Bo Zhang. Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch[J]. Journal of Semiconductors, 2014, 35(2): 024007. doi: 10.1088/1674-4926/35/2/024007 X R Luo, X W Wang, G Y Hu, Y H Fan, K Zhou, Y C Luo, Y Fan, Z Y Zhang, Y Mei, B Zhang. Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch[J]. J. Semicond., 2014, 35(2): 024007. doi: 10.1088/1674-4926/35/2/024007.Export: BibTex EndNote
      Citation:
      Xiaorong Luo, Xiaowei Wang, Gangyi Hu, Yuanhang Fan, Kun Zhou, Yinchun Luo, Ye Fan, Zhengyuan Zhang, Yong Mei, Bo Zhang. Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch[J]. Journal of Semiconductors, 2014, 35(2): 024007. doi: 10.1088/1674-4926/35/2/024007

      X R Luo, X W Wang, G Y Hu, Y H Fan, K Zhou, Y C Luo, Y Fan, Z Y Zhang, Y Mei, B Zhang. Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch[J]. J. Semicond., 2014, 35(2): 024007. doi: 10.1088/1674-4926/35/2/024007.
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      Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

      doi: 10.1088/1674-4926/35/2/024007
      Funds:

      the National Natural Science Foundation of China 61176069

      the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing 2012T50771

      the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing XM2012004

      Projects supported by the National Natural Science Foundation of China (No. 61176069), and the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing (Nos. 2012T50771, XM2012004)

      More Information
      • Corresponding author: Luo Xiaorong, xrluo@uestc.edu.cn
      • Received Date: 2013-07-12
      • Revised Date: 2013-08-07
      • Published Date: 2014-02-01

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