SEMICONDUCTOR INTEGRATED CIRCUITS

A self-biased PLL with low power and compact area

Hailong Jia, Xianmin Chen, Qi Liu and Guangtao Feng

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 Corresponding author: Jia Hailong, hljia@semi.ac.cn

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Abstract: A new low power, low phase jitter, compact realization, and self-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced.The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents.Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively.By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved.The PLL consumes 4.2 mW of power under 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mm2 (180×110 μm2), and the typical period jitter (RMS) is around 2.8 ps.

Key words: self-biased PLLring VCOlow powercompact area



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Fig. 1.  The main building blocks of general PLLs.

Fig. 2.  The proposed self-biased PLL structure.

Fig. 3.  The proposed VCO with supply regulation.

Fig. 4.  The charge pump with self-biased current.

Fig. 5.  The divide-by-2/3 cell with MS mode.

Fig. 6.  The successive division ratio MMD structure.

Fig. 7.  Die micrograph of the proposed PLL.

Fig. 8.  Measured period jitter results.

Fig. 9.  Relationship between VCO frequency,loop bandwidth and $V_{\rm ctrl}$.

Table 1.   Performance comparison.

ParameterReference [4]Reference [5]Reference [6]This work
Technology (nm) 65 65 65 40
Area ($\mu $m$^{2})$ 240 $\times $ 190 170 $\times $ 150 270 $\times $ 80 180 $\times $ 110
Frequency tuning range (GHz) 0.2-4 3 0.5-1.6 0.5-2.5
Power (mW/GHz) 3.86 0.66 1.33 1.75
Period jitter RMS (ps) 1.45 1.13 1.81 2.8
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    Received: 30 March 2015 Revised: Online: Published: 01 October 2015

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      Hailong Jia, Xianmin Chen, Qi Liu, Guangtao Feng. A self-biased PLL with low power and compact area[J]. Journal of Semiconductors, 2015, 36(10): 105007. doi: 10.1088/1674-4926/36/10/105007 H L Jia, X M Chen, Q Liu, G T Feng. A self-biased PLL with low power and compact area[J]. J. Semicond., 2015, 36(10): 105007. doi: 10.1088/1674-4926/36/10/105007.Export: BibTex EndNote
      Citation:
      Hailong Jia, Xianmin Chen, Qi Liu, Guangtao Feng. A self-biased PLL with low power and compact area[J]. Journal of Semiconductors, 2015, 36(10): 105007. doi: 10.1088/1674-4926/36/10/105007

      H L Jia, X M Chen, Q Liu, G T Feng. A self-biased PLL with low power and compact area[J]. J. Semicond., 2015, 36(10): 105007. doi: 10.1088/1674-4926/36/10/105007.
      Export: BibTex EndNote

      A self-biased PLL with low power and compact area

      doi: 10.1088/1674-4926/36/10/105007
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      • Corresponding author: Jia Hailong, hljia@semi.ac.cn
      • Received Date: 2015-03-30
      • Accepted Date: 2015-05-25
      • Published Date: 2015-01-25

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