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Digital post-calibration of a 5-bit 1.25 GS/s flash ADC

Yang Yang, Zhao Xianli, Zhong Shun'an and Li Guofeng

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Abstract: We report a high-speed flash analog to digital converter (ADC) linearization technique employing the inverse Volterra model and digital post processing. First, a 1.25 GS/s 5-bit flash ADC is designed using a 0.18 μm CMOS, and the signal is quantized by a distributed track-and-hold circuit. Second, based on the Volterra series, a proposed digital post-calibration model is introduced. Then, the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC. Simulation results indicate that the distortion is reduced effectively. Specifically, the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.

Key words: flash ADCVolterra seriesdigital post-calibration

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    Received: 20 August 2015 Revised: 19 September 2011 Online: Published: 01 February 2012

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      Yang Yang, Zhao Xianli, Zhong Shun'an, Li Guofeng. Digital post-calibration of a 5-bit 1.25 GS/s flash ADC[J]. Journal of Semiconductors, 2012, 33(2): 025011. doi: 10.1088/1674-4926/33/2/025011 Yang Y, Zhao X L, Zhong S, Li G F. Digital post-calibration of a 5-bit 1.25 GS/s flash ADC[J]. J. Semicond., 2012, 33(2): 025011. doi: 10.1088/1674-4926/33/2/025011.Export: BibTex EndNote
      Citation:
      Yang Yang, Zhao Xianli, Zhong Shun'an, Li Guofeng. Digital post-calibration of a 5-bit 1.25 GS/s flash ADC[J]. Journal of Semiconductors, 2012, 33(2): 025011. doi: 10.1088/1674-4926/33/2/025011

      Yang Y, Zhao X L, Zhong S, Li G F. Digital post-calibration of a 5-bit 1.25 GS/s flash ADC[J]. J. Semicond., 2012, 33(2): 025011. doi: 10.1088/1674-4926/33/2/025011.
      Export: BibTex EndNote

      Digital post-calibration of a 5-bit 1.25 GS/s flash ADC

      doi: 10.1088/1674-4926/33/2/025011
      • Received Date: 2015-08-20
      • Accepted Date: 2011-08-05
      • Revised Date: 2011-09-19
      • Published Date: 2012-01-20

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