SEMICONDUCTOR DEVICES

Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor

Yongye Liang1, 2, Kyungsoo Jang2, S. Velumani3, Cam Phu Thi Nguyen2 and Junsin Yi2

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 Corresponding author: Junsin Yi, E-mail: yi@yurim.skku.ac.kr

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Abstract: We reported the influence of interface trap density (Nt) on the electrical properties of amorphous InSnZnO based thin-film transistors, which were fabricated at different direct-current (DC) magnetron sputtering powers. The device with the smallest Nt of 5.68 × 1011 cm-2 and low resistivity of 1.21 × 10-3 Ω · cm exhibited a turn-on voltage (VON) of -3.60 V, a sub-threshold swing (S.S) of 0.16 V/dec and an on-off ratio (ION/IOFF) of ~ 8 × 108. With increasing Nt, the VON, S.S and ION/IOFF were suppressed to —9.40 V, 0.24 V/dec and 2.59 × 108, respectively. The VTH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices. The result showed that the reduction in Nt contributes to an improvement in the electrical properties and stability.

Key words: a-ITZO TFTslow resistivityinterface trap densityelectrical propertieselectrical stability



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Fig. 1.  Schematic cross-sectional diagram of the a-ITZO TFT bottom-gate structure.

Fig. 2.  Transfer characteristics log($I_{\rm DS})$-$V_{\rm GS}$ at $V_{\rm DS}$ $=$ 10 V of a-ITZO TFTs for devices A, B and C.

Fig. 3.  The characteristic of input voltage-output current for all devices.

Fig. 4.  The changes in resistivity as a function of sputtering power.

Fig. 5.  Electrical properties of a-ITZO-based TFTs as a function of sputtering power.

Fig. 6.  Transfer curves as a function of NGBS for devices A, B and C.

Fig. 7.  (a) The $V_{\rm TH}$ shift with gate bias stress time for all devices. (b) The SS shift with gate bias stress time for all devices.

Table 1.   Comparison of the extracted electrical properties including SS, $V_{\rm ON}$, $V_{\rm TH}$, $I_{\rm ON}$/$I_{\rm OFF}$, $N_{\rm t}$ and $\rho$.

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    Received: 29 July 2014 Revised: Online: Published: 01 February 2015

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      Yongye Liang, Kyungsoo Jang, S. Velumani, Cam Phu Thi Nguyen, Junsin Yi. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor[J]. Journal of Semiconductors, 2015, 36(2): 024007. doi: 10.1088/1674-4926/36/2/024007 Y Y Liang, K Jang, S. Velumani, C P T Nguyen, J. Yi. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor[J]. J. Semicond., 2015, 36(2): 024007. doi:  10.1088/1674-4926/36/2/024007.Export: BibTex EndNote
      Citation:
      Yongye Liang, Kyungsoo Jang, S. Velumani, Cam Phu Thi Nguyen, Junsin Yi. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor[J]. Journal of Semiconductors, 2015, 36(2): 024007. doi: 10.1088/1674-4926/36/2/024007

      Y Y Liang, K Jang, S. Velumani, C P T Nguyen, J. Yi. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor[J]. J. Semicond., 2015, 36(2): 024007. doi:  10.1088/1674-4926/36/2/024007.
      Export: BibTex EndNote

      Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor

      doi: 10.1088/1674-4926/36/2/024007
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      • Corresponding author: E-mail: yi@yurim.skku.ac.kr
      • Received Date: 2014-07-29
      • Accepted Date: 2014-09-15
      • Published Date: 2015-01-25

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