SEMICONDUCTOR DEVICES

Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory

Xinkai Li, Zongliang Huo, Lei Jin, Dandan Jiang, Peizhen Hong, Qiang Xu, Zhaoyun Tang, Chunlong Li and Tianchun Ye

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 Corresponding author: Huo Zongliang, huozongliang@ime.ac.cn

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Abstract: This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

Key words: 3D charge trapping devicesvertical charge losslateral charge migrationsemiconductor device simulation



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Fig1.  Schematic view of a cylindrical junction-less NAND string with three cells and two select transistors investigated in this paper. The main cell and string parameters are highlighted.

Fig2.  Band diagram during (a) program operation and (b) retention. The models include: ① trapping and de-trapping ② drift transport ③ barrier tunneling.

Fig3.  (Color online) The initial BTO electric field near the substrate side and initial TPO electric field away from the substrate side versus the channel radius. $V_{\rm g}$ $=$ 12 V.

Fig4.  (Color online) (a) Electric field distribution and (b) conduction band diagram of different channel radius devices at the programmed state.

Fig5.  Program threshold voltage shifts of 3D CTM devices with different gate lengths.

Fig6.  (a) Electric field profiles at the interface of channel and BTO along the channel direction at the beginning of program operation. (b) Maximum electric field at the interface of channel and BTO versus gate lengths.

Fig7.  Schematic diagram of electric field distribution with different gate lengths at the programming state.

Fig8.  Simulation of retention loss at 85 $^\circ C$ related only to lateral migration with different gate lengths. The inset gives the schematic diagram of lateral trapped charge profile evolution.

Fig9.  Program threshold voltage shifts of 3D CTM devices with different spacer lengths.

Fig10.  Electric field profiles at the interface of channel and BTO along the channel direction at the beginning of program operation.

Fig11.  $\Delta V_{\rm th}$ of cell 2 after 10 years versus the spacer lengths with cell~1 programmed.

Fig12.  Comparison of threshold voltage change caused by lateral charge migration between TCAT-type device and BiCS-type device.

Fig13.  Simulated lateral charge profile evolution (cutline at middle of CTL along the channel direction) at different retention time.

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Table 1.   Main parameters used in the simulation.

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    Received: 07 January 2015 Revised: Online: Published: 01 September 2015

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      Xinkai Li, Zongliang Huo, Lei Jin, Dandan Jiang, Peizhen Hong, Qiang Xu, Zhaoyun Tang, Chunlong Li, Tianchun Ye. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory[J]. Journal of Semiconductors, 2015, 36(9): 094008. doi: 10.1088/1674-4926/36/9/094008 X K Li, Z L Huo, L Jin, Dandan Jiang and A Jiang, P Z Hong, Q Xu, Z Y Tang, C L Li, T C Ye. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory[J]. J. Semicond., 2015, 36(9): 094008. doi: 10.1088/1674-4926/36/9/094008.Export: BibTex EndNote
      Citation:
      Xinkai Li, Zongliang Huo, Lei Jin, Dandan Jiang, Peizhen Hong, Qiang Xu, Zhaoyun Tang, Chunlong Li, Tianchun Ye. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory[J]. Journal of Semiconductors, 2015, 36(9): 094008. doi: 10.1088/1674-4926/36/9/094008

      X K Li, Z L Huo, L Jin, Dandan Jiang and A Jiang, P Z Hong, Q Xu, Z Y Tang, C L Li, T C Ye. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory[J]. J. Semicond., 2015, 36(9): 094008. doi: 10.1088/1674-4926/36/9/094008.
      Export: BibTex EndNote

      Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory

      doi: 10.1088/1674-4926/36/9/094008
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      Project supported by the National Natural Science Foundation of China (Nos. 61474137, 61176073, 61306107).

      More Information
      • Corresponding author: Huo Zongliang, huozongliang@ime.ac.cn
      • Received Date: 2015-01-07
      • Accepted Date: 2015-03-07
      • Published Date: 2015-01-25

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