SEMICONDUCTOR INTEGRATED CIRCUITS

A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators

Jixuan Xiang, Chixiao Chen, Fan Ye, Jun Xu, Ning Li and Junyan Ren

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 Corresponding author: Jun Xu, E-mail: jxu@fudan.edu.cn

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Abstract: This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of distributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to-noise plus distortion ratio (SNDR) is 32.13 dB and the spurious-free dynamic range (SFDR) is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.

Key words: SAR ADChigh speed2-b/stagenew switching procedureself-locking



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Fig. 1.  A block diagram of the 6-b 600 MS/s SAR ADC.

Fig. 2.  The new switching procedure for the 2-b/stage.

Fig. 3.  Waveforms of the top-plate signal at every stage.

Fig. 4.  (a) The conventional SAR ADCs' critical path. (b) The critical path of SAR with distributed topology. (c) The proposed scheme for the distributed comparators' topology.

Fig. 5.  The proposed disturbed comparators with self-locking.

Fig. 6.  The timing diagram of the self-locking process.

Fig. 7.  The circuits of the digital logic.

Fig. 8.  A chip photograph and circuit layout of the ADC.

Fig. 9.  The FFT spectrum at 5.6 MHz input.

Fig. 10.  SNDR and SFDR versus input frequency.

Fig. 11.  DNL and INL performance of the ADC.

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Table 1.   Performance summary.

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Table 2.   Performance comparison.

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    Received: 23 September 2014 Revised: Online: Published: 01 May 2015

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      Jixuan Xiang, Chixiao Chen, Fan Ye, Jun Xu, Ning Li, Junyan Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators[J]. Journal of Semiconductors, 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009 J X Xiang, C X Chen, F Ye, J Xu, N Li, J Y Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators[J]. J. Semicond., 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009.Export: BibTex EndNote
      Citation:
      Jixuan Xiang, Chixiao Chen, Fan Ye, Jun Xu, Ning Li, Junyan Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators[J]. Journal of Semiconductors, 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009

      J X Xiang, C X Chen, F Ye, J Xu, N Li, J Y Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators[J]. J. Semicond., 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009.
      Export: BibTex EndNote

      A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators

      doi: 10.1088/1674-4926/36/5/055009
      Funds:

      Project supported by the National High-Tech Research and Development Program of China (No.2013AA014101), and the National Science and Technology Program of China (No.2012BAI131307).

      More Information
      • Corresponding author: E-mail: jxu@fudan.edu.cn
      • Received Date: 2014-09-23
      • Accepted Date: 2014-11-20
      • Published Date: 2015-01-25

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