| Citation: |
Huang Yumei, Wang Jingguang, Wang Jinju, Hong Zhiliang. A Low Noise,High Linearity CMOS Receiver for 802.11b WLAN Applications[J]. Journal of Semiconductors, 2008, In Press.
Huang Y M, Wang J G, Wang J J, Hong Z L. A Low Noise,High Linearity CMOS Receiver for 802.11b WLAN Applications[J]. J. Semicond., 2008, 29(9): 1708.
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A Low Noise,High Linearity CMOS Receiver for 802.11b WLAN Applications
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Abstract
A 2.4GHz monolithic CMOS receiver with direct-conversion architecture is presented.This quadrature receiver is designed for 802.11b wireless LAN applications at the maximum data rate of 11Mbps as a low-cost solution.Five key blocks,i.e.,a low noise amplifier (LNA),a down-conversion mixer,a variable gain amplifier,a low pass filter,and a DC-offset cancellation circuit,are designed based on system design and low noise high linearity considerations.The necessary auxiliary circuits are also included.Fabricated in SMIC 0.18μm 1p6m RF CMOS process,the receiver’s performance is measured as:4.1dB noise figure,-7.5dBm input third order intercept point (IIP3) for LNA & mixer at high gain setting,-14dBm IIP3 for the whole receiver,53dBc @30MHz offset of adjacent channel power rejection,and less than 5mV output DC-offset.The receiver consumes 44mA under a 1.8V power supply with I,Q two paths.-
Keywords:
- 80211b,
- wireless LAN,
- receiver,
- DC-offset cancellation,
- mixer
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References
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Proportional views
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