J. Semicond. > 2013, Volume 34 > Issue 6 > 066001, doi: 10.1088/1674-4926/34/6/066001
|

SEMICONDUCTOR TECHNOLOGY

Interconnects for nanoscale MOSFET technology:a review

Amit Chaudhry

+ Author Affiliations

 Corresponding author: Amit Chaudhry, Email:amit_chaudhry01@yahoo.com

PDF

Abstract: In this paper, a review of Cu/low-k, carbon nanotube (CNT), graphene nanoribbon (GNR) and optical based interconnect technologies has been done. Interconnect models, challenges and solutions have also been discussed. Of all the four technologies, CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies, despite some minor drawbacks. It is concluded that beyond 32 nm technology, a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.

Key words: Cu/low-k, 3D integration, electromigration, CNTs, graphene interconnects, comparisons



[1]
Moore G E. Cramming more components onto integrated circuits. Proc IEEE, 1998, 86(1):82 doi: 10.1109/JPROC.1998.658762
[2]
Wolf S. Silicon processing for the VLSI era:deep submicron process technology. Vol.4. California:Lattice Press, 2007
[3]
Sun S C. Process technologies for advanced metallization and interconnect systems. Proceedings of International Electron Devices Meetings (IEDM), 1997:765
[4]
Streiter R, Geẞner T, Wolf H. Geometrical optimization of multi level interconnects using Cu and low-k dielectrics. Microelectron Eng, 1997, 33(1-4):429 doi: 10.1016/S0167-9317(96)00074-3
[5]
Takaoa Y, Kudoa H, Mitania J, et al. A 0.11μm CMOS technology featuring copper and very low k interconnects with high performance and reliability. Microelectron Reliab, 2002, 42(1):15 doi: 10.1016/S0026-2714(01)00233-5
[6]
Kioussis D, Ryan E T, Madan A, et al. Optimization of porous ultra low-k dielectrics (k ≤ qslant 2.55) for 28 nm generation. Proceedings of IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[7]
Lee J, Ahn S H, Jung I, et al. Robust porous SiOCH (k=2.5) for 28 nm and beyond technology node. Proceedings of IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[8]
Gu X, Nemoto T, Tomita Y, et al. Cu single Damascene integration of an organic nonporous ultralow-fluorocarbon dielectric deposited by microwave-excited plasma-enhanced CVD. IEEE Trans Electron Devices, 2012, 59(5):1445 doi: 10.1109/TED.2012.2187659
[9]
Liu P T, Chang T C, Lin Z W, et al. Application of electron-beam illuminated low-k silicate to nanoscale interconnect technology. Proceedings of International Microprocesses and Nanotechnology Conference, 2003:29
[10]
Zhou H, Shi F G, Zhao B. Design and control of critical properties of low-k dielectrics for nanoscale interconnects. Proceedings of 7th International Conference on Solid-State and Integrated Circuits Technology, 2004:497
[11]
Lia C Y, Zhang D H, Luc P W, et al. Metal-organic chemical vapor deposited Cu interconnects for deep submicron integrated circuits. Thin Solid Films, 2005, 471(1/2):270
[12]
Nagaraj N S, Bonifield T, Singh A, et al. Interconnect modeling for copper/low-k technologies. Proceedings of 17th International Conference on VLSI Design, 2004:425
[13]
Bohr M T. Interconnect scaling-the real limiter to high performance ULSI. Proceedings of International Electron Devices Meeting, 1995:241
[14]
Wanga K, Horsfall A, Cuthbertson A, et al. Comparative study of novel barrier layers in ULSI Cu interconnects. Microelectron Eng, 2007, 84(11):2486 doi: 10.1016/j.mee.2007.05.018
[15]
Yang C C, Flaitz P, Lid B, et al. Co capping layers for Cu/low-k interconnects. Microelectron Eng, 2012, 92:79 doi: 10.1016/j.mee.2011.04.017
[16]
Delsol R, Jacquemina J P, Gregoire M, et al. Improved electrical and reliability performance of 65 nm interconnects with new barrier integration schemes. Microelectron Eng, 2006, 83(11/12):2377
[17]
Tsai D C, Huang Y L, Lin S R, et al. Characteristics of a 10 nm-thick (TiVCr)N multi-component diffusion barrier layer with high diffusion resistance for Cu interconnects. Surf Coatings Technol, 2011, 205(21/22):5064
[18]
Gerlich L, Ohsiek S, Klein C, et al. Ultrathin TaN/Ta barrier modifications to fulfill next technology node requirements. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[19]
Zschech E, Besser P R. Microstructure characterization of metal interconnects and barrier layers:status and future. Proceedings of the IEEE International Interconnect Technology Conference, 2000:233
[20]
Guedj C, Guillaumond J F, Arnaud L, et al. Influence of the sidewall diffusion barrier on the transport properties of advanced Cu/low-k interconnects. Microelectron Eng, 2005, 82(3/4):374
[21]
Ding S F, Xie Q, Chen F, et al. Investigation of ultra-thin Al2O3 film as Cu diffusion barrier on low-k (k=2.5) dielectrics. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[22]
Wu W, Yuan J S. Skin effect of on-chip copper interconnects on electromigration. Solid-State Electron, 2002, 46(12):2269 doi: 10.1016/S0038-1101(02)00232-0
[23]
Tan C M, Roy A. Electromigration in ULSI interconnects. Mater Sci Eng R, 2007, 58:1 doi: 10.1016/j.mser.2007.04.002
[24]
http://ewh.ieee.org/r5/denver/sscs/Presentations/2010_01_Gambino.pdf
[25]
Oates A S, Lee S C. Electromigration failure distributions of dual damascene Cu/low k interconnects. Microelectron Reliab, 2006, 46(9-11):1581 doi: 10.1016/j.microrel.2006.07.038
[26]
McCusker N D, Gamble H S, Armstrong B M. Surface electromigration in copper interconnects. 37th Annual IEEE International Reliability Physics Symposium, 1999:270
[27]
Li B, Sullivan T D, Lee T C, et al. Reliability challenges for copper interconnects. Microelectron Reliab, 2004, 44(3):365 doi: 10.1016/j.microrel.2003.11.004
[28]
Maekawa K, Mori K, Suzumura N, et al. Impact of Al in Cu alloy interconnects on electro and stress migration reliabilities. Microelectron Eng, 2008, 85(10):2137 doi: 10.1016/j.mee.2008.04.004
[29]
Kawasaki H, Lee C, Yu T K. Realistic electromigration lifetime projection of VLSI interconnects. Thin Solid Films, 1994, 253(1/2):508
[30]
Hu C K, Gignac L, Rosenberg R. Electromigration of Cu/low dielectric constant interconnects. Microelectron Reliab, 2006, 46(2-4):213 doi: 10.1016/j.microrel.2005.05.015
[31]
Gonzalez J L, Rubio A. Shape effect on electromigration in VLSI interconnects. Microelectron Reliab, 1997, 37(7):1073 doi: 10.1016/S0026-2714(96)00269-7
[32]
Hu C K, Luther B. Electromigration in two-level interconnects of Cu and Al alloys. Mater Chem Phys, 1995, 41(1):1 doi: 10.1016/0254-0584(95)01505-1
[33]
Ho P S, Lee K D, Yoon S, et al. Effect of low k dielectrics on electro migration reliability for Cu interconnects. Mater Sci Semicond Processing, 2004, 7(3):157 doi: 10.1016/j.mssp.2004.06.005
[34]
Goto K, Oka Y, Suzumura N, et al. The simplest modification of Cu diffusion barrier dielectrics to improve Cu/low-k interconnects reliability. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[35]
Arnaud L, Gonella R, Tartavel G, et al. Electromigration failure modes in damascene copper interconnects. Microelectron Reliab, 1998, 38(6-8):1029 doi: 10.1016/S0026-2714(98)00122-X
[36]
Arnaud L, Cacho F, Doyen L, et al. Analysis of electromigration induced early failures in Cu interconnects for 45 nm node. Microelectron Eng, 2010, 87(3):355 doi: 10.1016/j.mee.2009.06.014
[37]
Davis J A, Kaloyeros V R, Beylansky A, et al. Interconnect limits on gigascale integration (GSI) in the 21st century. Proc IEEE, 2001, 89(3):305 doi: 10.1109/5.915376
[38]
Ramm P, Klumpp A, Weber J, et al. 3D integration technology:status and application development. Proc ESSCIRC, 2010:9
[39]
Javey A, Guo J, Wang Q, et al. Ballistic carbon nanotube field-effect transistors. Nature, 2003, 424(7):654
[40]
Bailey C, Lu H. Interconnect technologies using carbon nanotubes:current status and future challenges. 34th International Spring Seminar on Electronics Technology (ISSE), 2011
[41]
Brun C, Franck P, Chong Y C, et al. Hybrid EM/circuit modeling for carbon nanotubes based interconnects. IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011:158
[42]
Li J, Ye Q, Cassell A, et al. Bottom-up approach for carbon nanotube interconnects. Appl Phys Lett, 2003, 82(15):2491 doi: 10.1063/1.1566791
[43]
Yang C, Chan P C H, Fu Y, et al. Copper/carbon nanotube composite interconnect for enhanced electromigration resistance. 58th Electronic Components and Technology Conference, 2008:412
[44]
Dijon J, Fournier A, Szkutnik P D, et al. Carbon nanotubes for interconnects in future integrated circuits:the challenge of the density. Diamond and Related Materials, 2010, 19(5/6):382
[45]
Li H, Yin W Y, Mao J F. Modeling of carbon nanotube interconnects and comparative analysis with Cu interconnects. Asia-Pacific Microwave Conference, 2006:1361
[46]
Rakheja S, Naeemi A. Modeling interconnects for post-CMOS devices and comparison with copper interconnects. IEEE Trans Electron Devices, 2011, 58(5):1319 doi: 10.1109/TED.2011.2109004
[47]
Ragheb T, Massoud Y. On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. IEEE/ACM International Conference on Computer-Aided Design, 2008:593
[48]
Li H, Xu C, Srivastava N, et al. Carbon nanomaterials for next-generation interconnects and passives:physics, status, and prospects. IEEE Trans Electron Devices, 2009, 56(9):1799 doi: 10.1109/TED.2009.2026524
[49]
Banerjee K, Li H, Xu C. Prospects of carbon nanomaterials in VLSI for interconnections and energy storage. 31st EOS/ESD Symposium, 2009:1
[50]
Murali R, Brenner K, Yang Y, et al. Resistivity of graphene nanoribbon interconnects. IEEE Electron Device Lett, 2009, 30(6):611 doi: 10.1109/LED.2009.2020182
[51]
Naeemi A, Meindl J D. Compact physics-based circuit models for graphene nanoribbon interconnects. IEEE Trans Electron Devices, 2009, 56(9):1822 doi: 10.1109/TED.2009.2026122
[52]
Yu T, Lee E K, Briggs B, et al. Reliability study of bilayer graphene-material for future transistor and interconnect. IEEE International Reliability Physics Symposium (IRPS), 2010:80
[53]
Das D, Rahaman H. Crosstalk and gate oxide reliability analysis in graphene nanoribbon interconnects. International Symposium on Electronic System Design (ISED), 2011:182
[54]
Xu C, Li H, Banerjee K. Graphene nano-ribbon (GNR) interconnects:a genuine contender or a delusive dream. IEEE International Electron Devices Meeting, 2008:1
[55]
Haurylau M, Chen G, Chen H, et al. On-chip optical interconnect roadmap:challenges and critical directions. IEEE J Sel Topics Quantum Electron, 2006, 12(6):1699 doi: 10.1109/JSTQE.2006.880615
[56]
Kapur P, Saraswat K C. Optical interconnects for future high performance integrated circuits. Physica E:Low-Dimensional Systems and Nanostructures, 2003, 16(3/4):620
[57]
Wada K, Luan H C, Lim D R, et al. On-chip interconnection beyond semiconductor roadmap:silicon microphotonics. Proc SPIE, 2002, 4870:437 doi: 10.1117/12.475558
[58]
Banerjee K, Li H, Srivastava N. Current status and future perspectives of carbon nanotube interconnects. 8th IEEE Conference on Nanotechnology, 2008:432
[59]
Xu C, Li H, Banerjee K. Modeling, analysis, and design of graphene nano-ribbon interconnects. IEEE Trans Electron Devices, 2009, 56(8):1567 doi: 10.1109/TED.2009.2024254
[60]
Koo K H, Kapur P, Saraswat K C. Compact performance models and comparisons for gigascale on-chip global interconnect technologies. IEEE Trans Electron Devices, 2009, 56(9):1787 doi: 10.1109/TED.2009.2026196
[61]
Srivastava N, Li H, Kreupl F, et al. On the applicability of single-walled carbon nanotubes as VLSI interconnects. IEEE Trans Nanotechnol, 2009, 8(4):542 doi: 10.1109/TNANO.2009.2013945
[62]
Awano Y. Graphene for VLSI:FET and interconnect applications. Proceedings of International Electron Devices Meeting (IEDM), 2009:1
Fig. 1.  Delay as a function of feature size[3]

DownLoad: Full-Size Img PowerPoint
Fig. 2.  SEM image of a metallic interconnect[5]

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Schematic of process sequence for bottom-up fabrication of CNT bundle vias[42]

DownLoad: Full-Size Img PowerPoint
Fig. 4.  SEM image of GNRs between each electrode pair[50]

DownLoad: Full-Size Img PowerPoint
Fig. 5.  A crossectional SEM image of a silicon waveguide[57]

DownLoad: Full-Size Img PowerPoint

Table 1.   Cu/low-k interconnect roadmap[24]

Table 2.   Comparison chart of four interconnect technologies
[1]
Moore G E. Cramming more components onto integrated circuits. Proc IEEE, 1998, 86(1):82 doi: 10.1109/JPROC.1998.658762
[2]
Wolf S. Silicon processing for the VLSI era:deep submicron process technology. Vol.4. California:Lattice Press, 2007
[3]
Sun S C. Process technologies for advanced metallization and interconnect systems. Proceedings of International Electron Devices Meetings (IEDM), 1997:765
[4]
Streiter R, Geẞner T, Wolf H. Geometrical optimization of multi level interconnects using Cu and low-k dielectrics. Microelectron Eng, 1997, 33(1-4):429 doi: 10.1016/S0167-9317(96)00074-3
[5]
Takaoa Y, Kudoa H, Mitania J, et al. A 0.11μm CMOS technology featuring copper and very low k interconnects with high performance and reliability. Microelectron Reliab, 2002, 42(1):15 doi: 10.1016/S0026-2714(01)00233-5
[6]
Kioussis D, Ryan E T, Madan A, et al. Optimization of porous ultra low-k dielectrics (k ≤ qslant 2.55) for 28 nm generation. Proceedings of IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[7]
Lee J, Ahn S H, Jung I, et al. Robust porous SiOCH (k=2.5) for 28 nm and beyond technology node. Proceedings of IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[8]
Gu X, Nemoto T, Tomita Y, et al. Cu single Damascene integration of an organic nonporous ultralow-fluorocarbon dielectric deposited by microwave-excited plasma-enhanced CVD. IEEE Trans Electron Devices, 2012, 59(5):1445 doi: 10.1109/TED.2012.2187659
[9]
Liu P T, Chang T C, Lin Z W, et al. Application of electron-beam illuminated low-k silicate to nanoscale interconnect technology. Proceedings of International Microprocesses and Nanotechnology Conference, 2003:29
[10]
Zhou H, Shi F G, Zhao B. Design and control of critical properties of low-k dielectrics for nanoscale interconnects. Proceedings of 7th International Conference on Solid-State and Integrated Circuits Technology, 2004:497
[11]
Lia C Y, Zhang D H, Luc P W, et al. Metal-organic chemical vapor deposited Cu interconnects for deep submicron integrated circuits. Thin Solid Films, 2005, 471(1/2):270
[12]
Nagaraj N S, Bonifield T, Singh A, et al. Interconnect modeling for copper/low-k technologies. Proceedings of 17th International Conference on VLSI Design, 2004:425
[13]
Bohr M T. Interconnect scaling-the real limiter to high performance ULSI. Proceedings of International Electron Devices Meeting, 1995:241
[14]
Wanga K, Horsfall A, Cuthbertson A, et al. Comparative study of novel barrier layers in ULSI Cu interconnects. Microelectron Eng, 2007, 84(11):2486 doi: 10.1016/j.mee.2007.05.018
[15]
Yang C C, Flaitz P, Lid B, et al. Co capping layers for Cu/low-k interconnects. Microelectron Eng, 2012, 92:79 doi: 10.1016/j.mee.2011.04.017
[16]
Delsol R, Jacquemina J P, Gregoire M, et al. Improved electrical and reliability performance of 65 nm interconnects with new barrier integration schemes. Microelectron Eng, 2006, 83(11/12):2377
[17]
Tsai D C, Huang Y L, Lin S R, et al. Characteristics of a 10 nm-thick (TiVCr)N multi-component diffusion barrier layer with high diffusion resistance for Cu interconnects. Surf Coatings Technol, 2011, 205(21/22):5064
[18]
Gerlich L, Ohsiek S, Klein C, et al. Ultrathin TaN/Ta barrier modifications to fulfill next technology node requirements. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[19]
Zschech E, Besser P R. Microstructure characterization of metal interconnects and barrier layers:status and future. Proceedings of the IEEE International Interconnect Technology Conference, 2000:233
[20]
Guedj C, Guillaumond J F, Arnaud L, et al. Influence of the sidewall diffusion barrier on the transport properties of advanced Cu/low-k interconnects. Microelectron Eng, 2005, 82(3/4):374
[21]
Ding S F, Xie Q, Chen F, et al. Investigation of ultra-thin Al2O3 film as Cu diffusion barrier on low-k (k=2.5) dielectrics. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[22]
Wu W, Yuan J S. Skin effect of on-chip copper interconnects on electromigration. Solid-State Electron, 2002, 46(12):2269 doi: 10.1016/S0038-1101(02)00232-0
[23]
Tan C M, Roy A. Electromigration in ULSI interconnects. Mater Sci Eng R, 2007, 58:1 doi: 10.1016/j.mser.2007.04.002
[24]
http://ewh.ieee.org/r5/denver/sscs/Presentations/2010_01_Gambino.pdf
[25]
Oates A S, Lee S C. Electromigration failure distributions of dual damascene Cu/low k interconnects. Microelectron Reliab, 2006, 46(9-11):1581 doi: 10.1016/j.microrel.2006.07.038
[26]
McCusker N D, Gamble H S, Armstrong B M. Surface electromigration in copper interconnects. 37th Annual IEEE International Reliability Physics Symposium, 1999:270
[27]
Li B, Sullivan T D, Lee T C, et al. Reliability challenges for copper interconnects. Microelectron Reliab, 2004, 44(3):365 doi: 10.1016/j.microrel.2003.11.004
[28]
Maekawa K, Mori K, Suzumura N, et al. Impact of Al in Cu alloy interconnects on electro and stress migration reliabilities. Microelectron Eng, 2008, 85(10):2137 doi: 10.1016/j.mee.2008.04.004
[29]
Kawasaki H, Lee C, Yu T K. Realistic electromigration lifetime projection of VLSI interconnects. Thin Solid Films, 1994, 253(1/2):508
[30]
Hu C K, Gignac L, Rosenberg R. Electromigration of Cu/low dielectric constant interconnects. Microelectron Reliab, 2006, 46(2-4):213 doi: 10.1016/j.microrel.2005.05.015
[31]
Gonzalez J L, Rubio A. Shape effect on electromigration in VLSI interconnects. Microelectron Reliab, 1997, 37(7):1073 doi: 10.1016/S0026-2714(96)00269-7
[32]
Hu C K, Luther B. Electromigration in two-level interconnects of Cu and Al alloys. Mater Chem Phys, 1995, 41(1):1 doi: 10.1016/0254-0584(95)01505-1
[33]
Ho P S, Lee K D, Yoon S, et al. Effect of low k dielectrics on electro migration reliability for Cu interconnects. Mater Sci Semicond Processing, 2004, 7(3):157 doi: 10.1016/j.mssp.2004.06.005
[34]
Goto K, Oka Y, Suzumura N, et al. The simplest modification of Cu diffusion barrier dielectrics to improve Cu/low-k interconnects reliability. IEEE International Interconnect Technology Conference and Materials for Advanced Metallization (ⅡTC/MAM), 2011
[35]
Arnaud L, Gonella R, Tartavel G, et al. Electromigration failure modes in damascene copper interconnects. Microelectron Reliab, 1998, 38(6-8):1029 doi: 10.1016/S0026-2714(98)00122-X
[36]
Arnaud L, Cacho F, Doyen L, et al. Analysis of electromigration induced early failures in Cu interconnects for 45 nm node. Microelectron Eng, 2010, 87(3):355 doi: 10.1016/j.mee.2009.06.014
[37]
Davis J A, Kaloyeros V R, Beylansky A, et al. Interconnect limits on gigascale integration (GSI) in the 21st century. Proc IEEE, 2001, 89(3):305 doi: 10.1109/5.915376
[38]
Ramm P, Klumpp A, Weber J, et al. 3D integration technology:status and application development. Proc ESSCIRC, 2010:9
[39]
Javey A, Guo J, Wang Q, et al. Ballistic carbon nanotube field-effect transistors. Nature, 2003, 424(7):654
[40]
Bailey C, Lu H. Interconnect technologies using carbon nanotubes:current status and future challenges. 34th International Spring Seminar on Electronics Technology (ISSE), 2011
[41]
Brun C, Franck P, Chong Y C, et al. Hybrid EM/circuit modeling for carbon nanotubes based interconnects. IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011:158
[42]
Li J, Ye Q, Cassell A, et al. Bottom-up approach for carbon nanotube interconnects. Appl Phys Lett, 2003, 82(15):2491 doi: 10.1063/1.1566791
[43]
Yang C, Chan P C H, Fu Y, et al. Copper/carbon nanotube composite interconnect for enhanced electromigration resistance. 58th Electronic Components and Technology Conference, 2008:412
[44]
Dijon J, Fournier A, Szkutnik P D, et al. Carbon nanotubes for interconnects in future integrated circuits:the challenge of the density. Diamond and Related Materials, 2010, 19(5/6):382
[45]
Li H, Yin W Y, Mao J F. Modeling of carbon nanotube interconnects and comparative analysis with Cu interconnects. Asia-Pacific Microwave Conference, 2006:1361
[46]
Rakheja S, Naeemi A. Modeling interconnects for post-CMOS devices and comparison with copper interconnects. IEEE Trans Electron Devices, 2011, 58(5):1319 doi: 10.1109/TED.2011.2109004
[47]
Ragheb T, Massoud Y. On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. IEEE/ACM International Conference on Computer-Aided Design, 2008:593
[48]
Li H, Xu C, Srivastava N, et al. Carbon nanomaterials for next-generation interconnects and passives:physics, status, and prospects. IEEE Trans Electron Devices, 2009, 56(9):1799 doi: 10.1109/TED.2009.2026524
[49]
Banerjee K, Li H, Xu C. Prospects of carbon nanomaterials in VLSI for interconnections and energy storage. 31st EOS/ESD Symposium, 2009:1
[50]
Murali R, Brenner K, Yang Y, et al. Resistivity of graphene nanoribbon interconnects. IEEE Electron Device Lett, 2009, 30(6):611 doi: 10.1109/LED.2009.2020182
[51]
Naeemi A, Meindl J D. Compact physics-based circuit models for graphene nanoribbon interconnects. IEEE Trans Electron Devices, 2009, 56(9):1822 doi: 10.1109/TED.2009.2026122
[52]
Yu T, Lee E K, Briggs B, et al. Reliability study of bilayer graphene-material for future transistor and interconnect. IEEE International Reliability Physics Symposium (IRPS), 2010:80
[53]
Das D, Rahaman H. Crosstalk and gate oxide reliability analysis in graphene nanoribbon interconnects. International Symposium on Electronic System Design (ISED), 2011:182
[54]
Xu C, Li H, Banerjee K. Graphene nano-ribbon (GNR) interconnects:a genuine contender or a delusive dream. IEEE International Electron Devices Meeting, 2008:1
[55]
Haurylau M, Chen G, Chen H, et al. On-chip optical interconnect roadmap:challenges and critical directions. IEEE J Sel Topics Quantum Electron, 2006, 12(6):1699 doi: 10.1109/JSTQE.2006.880615
[56]
Kapur P, Saraswat K C. Optical interconnects for future high performance integrated circuits. Physica E:Low-Dimensional Systems and Nanostructures, 2003, 16(3/4):620
[57]
Wada K, Luan H C, Lim D R, et al. On-chip interconnection beyond semiconductor roadmap:silicon microphotonics. Proc SPIE, 2002, 4870:437 doi: 10.1117/12.475558
[58]
Banerjee K, Li H, Srivastava N. Current status and future perspectives of carbon nanotube interconnects. 8th IEEE Conference on Nanotechnology, 2008:432
[59]
Xu C, Li H, Banerjee K. Modeling, analysis, and design of graphene nano-ribbon interconnects. IEEE Trans Electron Devices, 2009, 56(8):1567 doi: 10.1109/TED.2009.2024254
[60]
Koo K H, Kapur P, Saraswat K C. Compact performance models and comparisons for gigascale on-chip global interconnect technologies. IEEE Trans Electron Devices, 2009, 56(9):1787 doi: 10.1109/TED.2009.2026196
[61]
Srivastava N, Li H, Kreupl F, et al. On the applicability of single-walled carbon nanotubes as VLSI interconnects. IEEE Trans Nanotechnol, 2009, 8(4):542 doi: 10.1109/TNANO.2009.2013945
[62]
Awano Y. Graphene for VLSI:FET and interconnect applications. Proceedings of International Electron Devices Meeting (IEDM), 2009:1

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2881 Times PDF downloads: 77 Times Cited by: 0 Times

    History

    Received: 01 December 2012 Revised: 22 December 2012 Online: Published: 01 June 2013

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2013  >  34(6): 066001
      Amit Chaudhry. Interconnects for nanoscale MOSFET technology:a review[J]. Journal of Semiconductors, 2013, 34(6): 066001. doi: 10.1088/1674-4926/34/6/066001 A Chaudhry. Interconnects for nanoscale MOSFET technology:a review[J]. J. Semicond., 2013, 34(6): 066001. doi: 10.1088/1674-4926/34/6/066001.Export: BibTex EndNote
      Citation:
      Amit Chaudhry. Interconnects for nanoscale MOSFET technology:a review[J]. Journal of Semiconductors, 2013, 34(6): 066001. doi: 10.1088/1674-4926/34/6/066001

      A Chaudhry. Interconnects for nanoscale MOSFET technology:a review[J]. J. Semicond., 2013, 34(6): 066001. doi: 10.1088/1674-4926/34/6/066001.
      Export: BibTex EndNote
      shu

      Interconnects for nanoscale MOSFET technology:a review

      doi: 10.1088/1674-4926/34/6/066001

      • UIET, Panjab University, Chandigarh, India

      More Information
      • Corresponding author: Amit Chaudhry, Email:amit_chaudhry01@yahoo.com
      • Received Date: 2012-12-01
      • Revised Date: 2012-12-22
      • Published Date: 2013-06-01

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return