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Layout and process hot carrier optimization of HV-nLEDMOS transistor

Qian Qinsong, Li Haisong, Sun Weifeng and Yi Yangbo

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Abstract: Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

Key words: nLEDMOS

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    Received: 18 August 2015 Revised: 12 November 2008 Online: Published: 01 March 2009

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      Qian Qinsong, Li Haisong, Sun Weifeng, Yi Yangbo. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. Journal of Semiconductors, 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004 Qian Q S, Li H S, Sun W F, Yi Y B. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. J. Semicond., 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004.Export: BibTex EndNote
      Citation:
      Qian Qinsong, Li Haisong, Sun Weifeng, Yi Yangbo. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. Journal of Semiconductors, 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004

      Qian Q S, Li H S, Sun W F, Yi Y B. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. J. Semicond., 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004.
      Export: BibTex EndNote

      Layout and process hot carrier optimization of HV-nLEDMOS transistor

      doi: 10.1088/1674-4926/30/3/034004
      • Received Date: 2015-08-18
      • Accepted Date: 2008-04-19
      • Revised Date: 2008-11-12
      • Published Date: 2009-03-12

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