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An OPAMP with High DC Gain in 0.18μm Digital CMOS

Wang Han and Ye Qing

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Abstract: When scaled down to the ultra deep sub-micron field,the condition that the system-on-a-chip(SOC) needs analog circuits on the chip encounters serious challenges.Based on a SMIC 0.18μm digital process,the operational amplifier is designed with the gain-boosted,also with the bulk regulator.The design widens the input range.Furthermore,the performance limited by pipelined ADC is analyzed in detail.The simulated result shows an open-loop gain of over 100dB,an unit gain bandwidth of 322MHz with a 8.5pF load,and a power consumption of 1.9mW

Key words: CMOSoperational amplifierfolded-cascodegain-boosterbulk regulatorpipelined ADC

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    Received: 20 August 2015 Revised: Online: Published: 01 December 2006

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      Wang Han, Ye Qing. An OPAMP with High DC Gain in 0.18μm Digital CMOS[J]. Journal of Semiconductors, 2006, In Press. Wang H, Ye Q. An OPAMP with High DC Gain in 0.18μm Digital CMOS[J]. Chin. J. Semicond., 2006, 27(13): 318.Export: BibTex EndNote
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      Wang Han, Ye Qing. An OPAMP with High DC Gain in 0.18μm Digital CMOS[J]. Journal of Semiconductors, 2006, In Press.

      Wang H, Ye Q. An OPAMP with High DC Gain in 0.18μm Digital CMOS[J]. Chin. J. Semicond., 2006, 27(13): 318.
      Export: BibTex EndNote

      An OPAMP with High DC Gain in 0.18μm Digital CMOS

      • Received Date: 2015-08-20

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