Abstract: An energy-efficient and highly linear capacitor switching procedure for successive approximation register (SAR) ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known V_CM-based switching scheme. Moreover, the proposed method shows better linearity than the V_CM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18 μ m standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μ W at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion-step. The measured peak DNL and INL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL is observed at 1/4(V_FS) and 3/4(V_FS), the same as the static nonlinearity model.

Key words: analog-to-digital converter, capacitor switching procedure, switching energy, linearity, successive approximation register