SEMICONDUCTOR MATERIALS

Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization

Peihong Cheng1, 2, Shihua Huang1, and Fang Lu2

+ Author Affiliations

 Corresponding author: Huang Shihua, Email:huangshihua@zjnu.cn

PDF

Abstract: The rapid thermal annealing (RTA) nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature (usually 600-900℃) in the RTA process will worsen the performance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film (SINC), which is able to resolve the problems mentioned above. Compared with Ni nanocrystals (NCs) formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window (2.78 V) was observed for Ni NCs deposited by SINC at 300℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600℃. A large change (from 0.20 to 4.59 V) of the memory window was observed while the operation voltage increased from 0 to ±10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.

Key words: metal nanocrystal memorysynchronously crystallizationC-V characteristics



[1]
Tiwari S, Rana F, Hanafi H, et al. A silicon nanocrystals based memory. Appl Phys Lett, 1996, 68(10):1377 doi: 10.1063/1.116085
[2]
Ostraat M L, De Blauwe J W, Green M L, et al. Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices. Appl Phys Lett, 2001, 79(3):433 doi: 10.1063/1.1385190
[3]
Kwon Y H, Park C J, Lee W C, et al. Memory effects related to deep levels in metal-oxide-semiconductor structure with nanocrystalline Si. Appl Phys Lett, 2002, 80(14):2052 doi: 10.1063/1.1467617
[4]
Liu Z, Lee C, Narayanan V, et al. Metal nanocrystal memories, part Ⅰ:device design and fabrication. IEEE Trans Electron Devices, 2002, 49(9):1606 doi: 10.1109/TED.2002.802617
[5]
Park B, Cho K, Koo Y S, et al. Memory characteristics of platinum nanoparticle-embedded MOS capacitors. Current Appl Phys, 2009, 9(6):1334 doi: 10.1016/j.cap.2009.02.013
[6]
Lee D J, Yim S S, Kim K S, et al. Nonvolatile memory characteristics of atomic layer deposited Ru nanocrystals with a SiO2/Al2O3 bilayered tunnel barrier. J Appl Phys, 2010, 107(1):013707 doi: 10.1063/1.3275346
[7]
Lee J J, Harada Y, Pyun J W, et al. Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications. Appl Phys Lett, 2005, 86(10):103505 doi: 10.1063/1.1881778
[8]
Tan Z, Samanta S K, Yoo W J, et al. Self-assembly of Ni nanocrystals on HfO2 and N-assisted Ni confinement for nonvolatile memory application. Appl Phys Lett, 2005, 86(1):013107 doi: 10.1063/1.1846952
[9]
Sargentis C, Giannakopoulos K, Travlos A, et al. Simple method for the fabrication of a high dielectric constant metal-oxide-semiconductor capacitor embedded with Pt nanoparticles. Appl Phys Lett, 2006, 88(7):073106 doi: 10.1063/1.2174099
[10]
Carles R, Farcau C, Bonafos C, et al. The synthesis of single layers of Ag nanocrystals by ultra-low-energy ion implantation for large-scale plasmonic structures. Nanotechnology, 2009, 20(35):355305 doi: 10.1088/0957-4484/20/35/355305
[11]
Hong A J, Liu C C, Wang Y, et al. Metal nanodot memory by self-assembled block copolymer lift-off. Nano Lett, 2010, 10(1):224 doi: 10.1021/nl903340a
[12]
Zhu C, Huo Z, Xu Z, et al. Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-k trapping layer. Appl Phys Lett, 2010, 97(25):253503 doi: 10.1063/1.3531559
[13]
Stathis J H, DiMaria D J. Reliability projection for ultra-thin oxides at low voltage. Int Electron Dev Meeting, San Francisco, CA, 1998:167 http://ieeexplore.ieee.org/document/00746309/
[14]
Lo S H, Buchanan D A, Taur Y, et al. Modeling and characterization of n+-and p+-polysilicon-gate ultra-thin oxides (21-26 A). VLSI Symp Dig Tech Papers, Piscataway, NJ, 1997:149 http://ieeexplore.ieee.org/document/623742/?arnumber=623742&punumber%3D4913
[15]
Kang T K, Wang C C, Tsui B Y, et al. Selectivity investigation of HfO2 to oxide using wet etching. Proc Semicond Manuf Technol Workshop, San Francisco, CA, 2004:87
[16]
Zhao D, Zhu Y, Liu J. Charge storage in a metal-oxide-semiconductor capacitor containing cobalt nanocrystals. Solid State Electron, 2006, 50(6):268 http://cat.inist.fr/?aModele=afficheN&cpsidt=17499477
[17]
Kwon Y H, Park C J, Lee W C, et al. Memory effects related to deep levels in metal-oxide-semiconductor structure with nanocrystalline Si. Appl Phys Lett, 2002, 80(14):2502 doi: 10.1063/1.1467617
[18]
Schuegraf K F, Hu C. Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation. IEEE Trans Electron Devices, 1994, 41(5):761 doi: 10.1109/16.285029
[19]
Lee W C, Hu C. Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron and hole tunneling. IEEE Trans Electron Devices, 2001, 48(7):1366 doi: 10.1109/16.930653
[20]
Sze S M, Kwok K K N. Physics of semiconductor devices. 3rd ed. New Jersey: John Wiley & Sons, 2007: 134
Fig. 1.  Schematic cross-sectional structure of the MOS capacitor using metal NCs embedded between the silica and hafnium oxide layer as charge storage elements.

Fig. 2.  The SEM plane-view images of Ni NCs deposited using the SINC method at 300℃ while (a) a HfO2 cap layer was deposited, and (b) a HfO2cap layer was not deposited.

Fig. 3.  High-frequency (1 MHz) CV characteristic for MOS capacitor embedded with Ni NCs under different sweep bias voltages. The memory windows (0.65 and 2.78 V) were observed while the sweep voltages are ±4 and ±6 V, respectively. Counterclockwise hysteresis loops were observed, indicative of the distinct memory effect.

Fig. 4.  (a) CV hysteresis characteristics of MOS capacitors fabricated under different substrate temperatures. Memory windows, as a function of the different deposition temperatures of Ni film, are shown in the inset. (b) CV characteristics for reference MOS capacitor after RTA at different temperatures. The inset demonstrates the memory windows versus RTA temperature.

Fig. 5.  CV characteristics of the MOS capacitor as a function of different program (P) and erase (E) operations gate voltages at the stressing time of 1 s.

Fig. 6.  Dependence of the CV characteristic on various stressing times under ±8 V bias voltage. The asymmetrical positive and negative flat-band voltage shift is due to the different tunnel probability between electrons and holes

Fig. 7.  The amount of electrons or holes trapped by NCs as a function of stressing time. The simulating results are in agreement with the experimental measurements.

[1]
Tiwari S, Rana F, Hanafi H, et al. A silicon nanocrystals based memory. Appl Phys Lett, 1996, 68(10):1377 doi: 10.1063/1.116085
[2]
Ostraat M L, De Blauwe J W, Green M L, et al. Synthesis and characterization of aerosol silicon nanocrystal nonvolatile floating-gate memory devices. Appl Phys Lett, 2001, 79(3):433 doi: 10.1063/1.1385190
[3]
Kwon Y H, Park C J, Lee W C, et al. Memory effects related to deep levels in metal-oxide-semiconductor structure with nanocrystalline Si. Appl Phys Lett, 2002, 80(14):2052 doi: 10.1063/1.1467617
[4]
Liu Z, Lee C, Narayanan V, et al. Metal nanocrystal memories, part Ⅰ:device design and fabrication. IEEE Trans Electron Devices, 2002, 49(9):1606 doi: 10.1109/TED.2002.802617
[5]
Park B, Cho K, Koo Y S, et al. Memory characteristics of platinum nanoparticle-embedded MOS capacitors. Current Appl Phys, 2009, 9(6):1334 doi: 10.1016/j.cap.2009.02.013
[6]
Lee D J, Yim S S, Kim K S, et al. Nonvolatile memory characteristics of atomic layer deposited Ru nanocrystals with a SiO2/Al2O3 bilayered tunnel barrier. J Appl Phys, 2010, 107(1):013707 doi: 10.1063/1.3275346
[7]
Lee J J, Harada Y, Pyun J W, et al. Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications. Appl Phys Lett, 2005, 86(10):103505 doi: 10.1063/1.1881778
[8]
Tan Z, Samanta S K, Yoo W J, et al. Self-assembly of Ni nanocrystals on HfO2 and N-assisted Ni confinement for nonvolatile memory application. Appl Phys Lett, 2005, 86(1):013107 doi: 10.1063/1.1846952
[9]
Sargentis C, Giannakopoulos K, Travlos A, et al. Simple method for the fabrication of a high dielectric constant metal-oxide-semiconductor capacitor embedded with Pt nanoparticles. Appl Phys Lett, 2006, 88(7):073106 doi: 10.1063/1.2174099
[10]
Carles R, Farcau C, Bonafos C, et al. The synthesis of single layers of Ag nanocrystals by ultra-low-energy ion implantation for large-scale plasmonic structures. Nanotechnology, 2009, 20(35):355305 doi: 10.1088/0957-4484/20/35/355305
[11]
Hong A J, Liu C C, Wang Y, et al. Metal nanodot memory by self-assembled block copolymer lift-off. Nano Lett, 2010, 10(1):224 doi: 10.1021/nl903340a
[12]
Zhu C, Huo Z, Xu Z, et al. Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-k trapping layer. Appl Phys Lett, 2010, 97(25):253503 doi: 10.1063/1.3531559
[13]
Stathis J H, DiMaria D J. Reliability projection for ultra-thin oxides at low voltage. Int Electron Dev Meeting, San Francisco, CA, 1998:167 http://ieeexplore.ieee.org/document/00746309/
[14]
Lo S H, Buchanan D A, Taur Y, et al. Modeling and characterization of n+-and p+-polysilicon-gate ultra-thin oxides (21-26 A). VLSI Symp Dig Tech Papers, Piscataway, NJ, 1997:149 http://ieeexplore.ieee.org/document/623742/?arnumber=623742&punumber%3D4913
[15]
Kang T K, Wang C C, Tsui B Y, et al. Selectivity investigation of HfO2 to oxide using wet etching. Proc Semicond Manuf Technol Workshop, San Francisco, CA, 2004:87
[16]
Zhao D, Zhu Y, Liu J. Charge storage in a metal-oxide-semiconductor capacitor containing cobalt nanocrystals. Solid State Electron, 2006, 50(6):268 http://cat.inist.fr/?aModele=afficheN&cpsidt=17499477
[17]
Kwon Y H, Park C J, Lee W C, et al. Memory effects related to deep levels in metal-oxide-semiconductor structure with nanocrystalline Si. Appl Phys Lett, 2002, 80(14):2502 doi: 10.1063/1.1467617
[18]
Schuegraf K F, Hu C. Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation. IEEE Trans Electron Devices, 1994, 41(5):761 doi: 10.1109/16.285029
[19]
Lee W C, Hu C. Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction-and valence-band electron and hole tunneling. IEEE Trans Electron Devices, 2001, 48(7):1366 doi: 10.1109/16.930653
[20]
Sze S M, Kwok K K N. Physics of semiconductor devices. 3rd ed. New Jersey: John Wiley & Sons, 2007: 134
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2095 Times PDF downloads: 18 Times Cited by: 0 Times

    History

    Received: 06 April 2014 Revised: 12 May 2014 Online: Published: 01 October 2014

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Peihong Cheng, Shihua Huang, Fang Lu. Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization[J]. Journal of Semiconductors, 2014, 35(10): 103002. doi: 10.1088/1674-4926/35/10/103002 P H Cheng, S H Huang, F Lu. Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization[J]. J. Semicond., 2014, 35(10): 103002. doi: 10.1088/1674-4926/35/10/103002.Export: BibTex EndNote
      Citation:
      Peihong Cheng, Shihua Huang, Fang Lu. Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization[J]. Journal of Semiconductors, 2014, 35(10): 103002. doi: 10.1088/1674-4926/35/10/103002

      P H Cheng, S H Huang, F Lu. Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization[J]. J. Semicond., 2014, 35(10): 103002. doi: 10.1088/1674-4926/35/10/103002.
      Export: BibTex EndNote

      Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization

      doi: 10.1088/1674-4926/35/10/103002
      Funds:

      Project supported by the National Natural Science Foundation of China (No. 61076055) and the Open Project Program of Surface Physics Laboratory (National Key Laboratory) of Fudan University (No. KL2011_04)

      the Open Project Program of Surface Physics Laboratory (National Key Laboratory) of Fudan University KL2011_04

      the National Natural Science Foundation of China 61076055

      More Information
      • Corresponding author: Huang Shihua, Email:huangshihua@zjnu.cn
      • Received Date: 2014-04-06
      • Revised Date: 2014-05-12
      • Published Date: 2014-10-01

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return