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An improved single-loop sigma-delta modulator for GSM applications

Li Hongyi, Wang Yuan, Jia Song and Zhang Xing

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Abstract: Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer. This paper presents an improved 4th-order 1-bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion. The modulator was fabricated in a 0.35 μ m CMOS process, and it achieve 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply. The performance satisfies the requirements of a GSM system.

Key words: sigma-delta modulator

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    Received: 20 August 2015 Revised: 14 April 2011 Online: Published: 01 September 2011

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      Li Hongyi, Wang Yuan, Jia Song, Zhang Xing. An improved single-loop sigma-delta modulator for GSM applications[J]. Journal of Semiconductors, 2011, 32(9): 095009. doi: 10.1088/1674-4926/32/9/095009 Li H Y, Wang Y, Jia S, Zhang X. An improved single-loop sigma-delta modulator for GSM applications[J]. J. Semicond., 2011, 32(9): 095009. doi: 10.1088/1674-4926/32/9/095009.Export: BibTex EndNote
      Citation:
      Li Hongyi, Wang Yuan, Jia Song, Zhang Xing. An improved single-loop sigma-delta modulator for GSM applications[J]. Journal of Semiconductors, 2011, 32(9): 095009. doi: 10.1088/1674-4926/32/9/095009

      Li H Y, Wang Y, Jia S, Zhang X. An improved single-loop sigma-delta modulator for GSM applications[J]. J. Semicond., 2011, 32(9): 095009. doi: 10.1088/1674-4926/32/9/095009.
      Export: BibTex EndNote

      An improved single-loop sigma-delta modulator for GSM applications

      doi: 10.1088/1674-4926/32/9/095009
      Funds:

      The National Science Fund for Distinguished Young Scholars

      • Received Date: 2015-08-20
      • Accepted Date: 2011-03-10
      • Revised Date: 2011-04-14
      • Published Date: 2011-08-31

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