| Citation: |
Zhang Changchun, Wang Zhigong, Shi Si, Li Wei. A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS[J]. Journal of Semiconductors, 2009, 30(5): 055007. doi: 10.1088/1674-4926/30/5/055007
Zhang C C, Wang Z G, Shi S, Li W. A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS[J]. J. Semicond., 2009, 30(5): 055007. doi: 10.1088/1674-4926/30/5/055007.
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A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS
doi: 10.1088/1674-4926/30/5/055007
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Abstract
A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5–20 Gb/s. The chip size is 875×640 m2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.-
Keywords:
- demultiplexer,
- latch,
- CML,
- design philosophy
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References
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Proportional views
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