SEMICONDUCTOR DEVICES

Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET

Sangeeta Singh, P. N. Kondekar and Pawan Pal

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 Corresponding author: Sangeeta Singh, Email: sangeeta.singh@iiitdmj.ac.in

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Abstract: We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n+ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.

Key words: negative capacitanceintrinsic gaintransconductance generation factorintrinsic bias boosting



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Fig. 1.  Schematic cross-sectional view of (a) JLTFET and (b) NC-JLTFET.

Fig. 2.  Qualitative comparison of the transfer characteristics for NC-JLTFET and JLTFET at different operating bias, $V_{\rm DS}$.

Fig. 3.  (a) Transconductance $(g_{\rm m})$ of NC-JLTFET and JLTFET at different operating bias $V_{\rm DS}$, (b) output resistance ($R_{\rm o}$) and output conductance ($g_{\rm o}$) for NC-JLTFET at $V_{\rm DS}$ $=$ 1 V, (c) intrinsic gain $(g_{\rm m}R_{\rm o})$ of NC-JLTFET and JLTFET for $V_{\rm DS}$ $=$ 1 V.

Fig. 4.  Transconductance generation factor ($g_{\rm m}/I_{\rm D}$) of the NC-JLTFET as a function of $V_{\rm GS}$ at $V_{\rm DS}$ $=$ 0.4 and 1 V.

Fig. 5.  Intrinsic gate delay and unity gain bandwidth ($f_{\rm T}$) of the NC-JLTFET as a function of $V_{\rm GS}$ at $V_{\rm DS}$ $=$ 1 V.

Fig. 6.  (Color online) Effect of control gate work-function variation on the transfer characteristics ($I_{\rm D}$--$V_{\rm GS}$) of NC-JLTEFT with $L_{\rm G}$ $=$ 20~nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm.

Fig. 7.  Demonstration of point SS, $I_{\rm ON}/I_{\rm OFF}$, threshold voltage ($V_{\rm TH}$) and DIBL variation as a function of control gate work-function with $L_{\rm G}$ $=$ 20 nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm.

Fig. 8.  (Color online) $I_{\rm D}$ versus the $V_{\rm GS}$ curve of the NC-JLTEFT with TiO$_{2}$ and PZT gate stack for fixed source gate work-function variation at $V_{\rm DS}$ $=$ 1 V.

Fig. 9.  Comparison of point SS, $I_{\rm ON}/I_{\rm OFF}$ ratio, threshold voltage $V_{\rm TH}$ and DIBL for fixed source gate work-function ($\phi_{\rm S}$) variation for NC-JLTFET with $L_{\rm G}$ $=$ 20 nm, $t_{\rm Si}$ $=$ 5 nm, $t_{\rm ox}$ $=$ 2 nm at $V_{\rm DS}$ $=$ 1 V.

Table 1.   Simulation parameters for conventional JL-TFET and NCJLTFET.

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    Received: 12 June 2015 Revised: Online: Published: 01 February 2016

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      Sangeeta Singh, P. N. Kondekar, Pawan Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. Journal of Semiconductors, 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003 S Singh, P. N. Kondekar, P Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. J. Semicond., 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003.Export: BibTex EndNote
      Citation:
      Sangeeta Singh, P. N. Kondekar, Pawan Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. Journal of Semiconductors, 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003

      S Singh, P. N. Kondekar, P Pal. Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET[J]. J. Semicond., 2016, 37(2): 024003. doi: 10.1088/1674-4926/37/2/024003.
      Export: BibTex EndNote

      Transient performance estimation of charge plasma based negative capacitance ewline junctionless tunnel FET

      doi: 10.1088/1674-4926/37/2/024003
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      • Corresponding author: Email: sangeeta.singh@iiitdmj.ac.in
      • Received Date: 2015-06-12
      • Published Date: 2016-01-25

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