| Citation: |
Zhang Li, Chi Baoyong, Yao Jinke, Wang Zhihua, Chen Hongyi. A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation[J]. Journal of Semiconductors, 2006, In Press.
Zhang L, Chi B Y, Yao J K, Wang Z H, Chen H Y. A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation[J]. Chin. J. Semicond., 2006, 27(12): 2106.
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A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation
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Abstract
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying(GMSK)modulation is presented.A pre-compensation fractional-N phase-locked loop(PLL)is adopted in the modulator.The transfer function of the type-II third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out.Methods to calibrate the important loop parameters are introduced.A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design.The designed circuits are simulated in a 0.18μm 1P6M CMOS process.The power consumption of the PLL is only about 11mW with the low power consideration in building blocks design,and the data rate of the modulator can reach 2Mb/s -
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