J. Semicond. > 2022, Volume 43 > Issue 10 > 102501, doi: 10.1088/1674-4926/43/10/102501
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ARTICLES

Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform

Hongchao Zhang1, Xiangyue Ma1, Chuanpeng Jiang1, Jialiang Yin1, Shuqin Lyu2, Shiyang Lu2, Xiantao Shang2, Bowen Man2, Cong Zhang2, Dandan Li2, Shuhui Li2, Wenjing Chen3, Hongxi Liu2, , Gefei Wang2, , Kaihua Cao1, 3, , Zhaohao Wang1 and Weisheng Zhao1, 3

+ Author Affiliations

 Corresponding author: Hongxi Liu, hongxi_liu@tmc-bj.cn; Gefei Wang, gefei_wang@tmc-bj.cn; Kaihua Cao, kaihua.cao@buaa.edu.cn

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Abstract: We demonstrate in-plane field-free-switching spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices that are capable of low switching current density, fast speed, high reliability, and, most importantly, manufactured uniformly by the 200-mm-wafer platform. The performance of the devices is systematically studied, including their magnetic properties, switching behaviors, endurance and data retention. The successful integration of SOT devices within the 200-mm-wafer manufacturing platform provides a feasible way to industrialize SOT MRAMs. It is expected to obtain excellent performance of the devices by further optimizing the MTJ film stacks and the corresponding fabrication processes in the future.

Key words: SOT MTJ, low switching current densities, 200-mm-wafer platform, endurance, data retention



[1]
Dieny B, Prejbeanu I L, Garello K, et al. Opportunities and challenges for spintronics in the microelectronics industry. Nat Electron, 2020, 3, 446 doi: 10.1038/s41928-020-0461-5
[2]
Apalkov D, Dieny B, Slaughter J M. Magnetoresistive random access memory. Proc IEEE, 2016, 104, 1796 doi: 10.1109/JPROC.2016.2590142
[3]
Zhang Y, Zhao W S, Klein J O, et al. Spintronics for low-power computing. 2014 Design, Automation & Test in Europe Conference & Exhibition, 2014, 1 doi: 10.7873/DATE.2014.316
[4]
Chiang H L, Wang J F, Chen T C, et al. Cold MRAM as a density booster for embedded NVM in advanced technology. 2021 Symposium on VLSI Technology, 2021, 1
[5]
Antonyan A, Pyo S, Jung H, et al. Embedded MRAM macro for eFlash replacement. 2018 IEEE International Symposium on Circuits and Systems, 2018, 1 doi: 10.1109/ISCAS.2018.8351201
[6]
Naik V B, Lee K, Yamane K, et al. Manufacturable 22nm FD-SOI embedded MRAM technology for industrial-grade MCU and IOT applications. 2019 IEEE International Electron Devices Meeting, 2019, 2.3.1 doi: 10.1109/IEDM19573.2019.8993454
[7]
Chang L, Fried D M, Hergenrother J, et al. Stable SRAM cell design for the 32 nm node and beyond. 2005 Symposium on VLSI Technology, 2005, 128 doi: 10.1109/.2005.1469239
[8]
Chen Y H, Chan W M, Wu W C, et al. A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. IEEE J Solid-State Circuits, 2015, 50, 170 doi: 10.1109/JSSC.2014.2349977
[9]
Thomas L, Jan G, Serrano-Guisan S, et al. STT-MRAM devices with low damping and moment optimized for LLC applications at Ox nodes. 2018 IEEE Int Electron Devices Meet IEDM, 2018, 27.3.1 doi: 10.1109/IEDM.2018.8614700
[10]
Wang K L, Alzate J G, Amiri P K. Low-power non-volatile spintronic memory: STT-RAM and beyond. J Phys D, 2013, 46, 074003 doi: 10.1088/0022-3727/46/7/074003
[11]
Wang S D, Lee H, Ebrahimi F, et al. Comparative evaluation of spin-transfer-torque and magnetoelectric random access memory. IEEE J Emerg Sel Top Circuits Syst, 2016, 6, 134 doi: 10.1109/JETCAS.2016.2547681
[12]
Endoh T. Nonvolatile logic and memory devices based on spintronics. 2015 IEEE International Symposium on Circuits and Systems, 2015, 13 doi: 10.1109/ISCAS.2015.7168558
[13]
Engel B N, Akerman J, Butcher B, et al. A 4-Mb toggle MRAM based on a novel bit and switching method. IEEE Trans Magn, 2005, 41, 132 doi: 10.1109/TMAG.2004.840847
[14]
Slonczewski J C. Current-driven excitation of magnetic multilayers. J Magn Magn Mater, 1996, 159, L1 doi: 10.1016/0304-8853(96)00062-5
[15]
Huai Y M, Albert F, Nguyen P, et al. Observation of spin-transfer switching in deep submicron-sized and low-resistance magnetic tunnel junctions. Appl Phys Lett, 2004, 84, 3118 doi: 10.1063/1.1707228
[16]
Stiles M D, Zangwill A. Anatomy of spin-transfer torque. Phys Rev B, 2002, 66, 014407 doi: 10.1103/physrevb.66.014407
[17]
Stiles M D, Miltat J. Spin-transfer torque and dynamics. In: Spin Dynamics in Confined Magnetic Structures III. Springer, 2006, 225 doi: 10.1007/10938171_7
[18]
Carboni R, Ambrogio S, Chen W, et al. Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory. 2016 IEEE International Electron Devices Meeting, 2016, 21.6.1 doi: 10.1109/IEDM.2016.7838468
[19]
Li J, Augustine C, Salahuddin S, et al. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. 2008 45th ACM/IEEE Design Automation Conference, 2008, 278
[20]
Mukhopadhyay S, Mahmoodi H, Roy K. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans Comput Aided Des Integr Circuits Syst, 2005, 24, 1859 doi: 10.1109/TCAD.2005.852295
[21]
Zhao W S, Zhang Y, Devolder T, et al. Failure and reliability analysis of STT-MRAM. Microelectron Reliab, 2012, 52, 1848 doi: 10.1016/j.microrel.2012.06.035
[22]
Shao Q M, Li P, Liu L Q, et al. Roadmap of spin–orbit torques. IEEE Trans Magn, 2021, 57, 800439 doi: 10.1109/TMAG.2021.3078583
[23]
Guo Z X, Yin J L, Bai Y, et al. Spintronics for energy-efficient computing: An overview and outlook. Proc IEEE, 2021, 109, 1398 doi: 10.1109/JPROC.2021.3084997
[24]
Zhu D Q, Guo Z X, Du A, et al. First demonstration of three terminal MRAM devices with immunity to magnetic fields and 10 ns field free switching by electrical manipulation of exchange bias. 2021 IEEE International Electron Devices Meeting, 2021, 17.5.1 doi: 10.1109/IEDM19574.2021.9720599
[25]
Fukami S, Anekawa T, Zhang C, et al. A spin–orbit torque switching scheme with collinear magnetic easy axis and current configuration. Nat Nanotechnol, 2016, 11, 621 doi: 10.1038/nnano.2016.29
[26]
Honjo H, Nguyen T V A, Watanabe T, et al. First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. 2019 IEEE International Electron Devices Meeting, 2019, 28.5.1 doi: 10.1109/IEDM19573.2019.8993443
[27]
Couet S, Rao S, Van Beek S, et al. BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning. 2021 Symposium on VLSI Technology, 2021, 1
[28]
Rahaman S Z, Wang I J, Wang D Y, et al. Size-dependent switching properties of spin-orbit torque MRAM with manufacturing-friendly 8-inch wafer-level uniformity. IEEE J Electron Devices Soc, 2020, 8, 163 doi: 10.1109/JEDS.2020.2971892
[29]
Lourembam J, Huang L S, Chen B J, et al. Multi-state magnetic tunnel junction programmable by nanosecond spin-orbit torque pulse sequence. Adv Electron Mater, 2021, 7, 2001133 doi: 10.1002/aelm.202001133
[30]
Chen G L, Wang I J, Yeh P S, et al. An 8kb spin-orbit-torque magnetic random-access memory. 2021 International Symposium on VLSI Technology, Systems and Applications, 2021, 1 doi: 10.1109/VLSI-TSA51926.2021.9440096
[31]
Pai C F, Liu L Q, Li Y, et al. Spin transfer torque devices utilizing the giant spin Hall effect of tungsten. Appl Phys Lett, 2012, 101, 122404 doi: 10.1063/1.4753947
[32]
Liu J, Ohkubo T, Mitani S, et al. Correlation between the spin Hall angle and the structural phases of early 5d transition metals. Appl Phys Lett, 2015, 107, 232408 doi: 10.1063/1.4937452
[33]
Embedded Memories Technology scaling & STT-MRAM for IoT & Automotive. IEEE International Electron Devices Meeting Archive, 2017
[34]
Das J, Alam S M, Bhanja S. Non-destructive variability tolerant differential read for non-volatile logic. 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, 2012, 178 doi: 10.1109/MWSCAS.2012.6291986
[35]
Li Z, Yan B N, Yang L, et al. A new self-reference sensing scheme for TLC MRAM. 2015 IEEE International Symposium on Circuits and Systems, 2015, 593 doi: 10.1109/ISCAS.2015.7168703
[36]
Yun J, Nadeau-Dostie B, Keim M, et al. MBIST supported multi step trim for reliable eMRAM sensing. 2020 IEEE International Test Conference, 2020, 1 doi: 10.1109/ITC44778.2020.9325218
[37]
Sun J Z. Spin-current interaction with a monodomain magnetic body: A model study. Phys Rev B, 2000, 62, 570 doi: 10.1103/physrevb.62.570
[38]
Zhu L J, Zhu L J, Shi S J, et al. Enhancing spin-orbit torque by strong interfacial scattering from ultrathin insertion layers. Phys Rev Appl, 2019, 11, 061004 doi: 10.1103/physrevapplied.11.061004
[39]
Lee K, Kang S H. Design consideration of magnetic tunnel junctions for reliable high-temperature operation of STT-MRAM. IEEE Trans Magn, 2010, 46, 1537 doi: 10.1109/TMAG.2010.2043645
[40]
Rahaman S Z, Wang I J, Chen T Y, et al. Pulse-width and temperature effect on the switching behavior of an etch-stop-on-MgO-barrier spin-orbit torque MRAM cell. IEEE Electron Device Lett, 2018, 39, 1306 doi: 10.1109/LED.2018.2856518
[41]
Liu L Q, Pai C F, Li Y, et al. Spin-torque switching with the giant spin Hall effect of tantalum. Science, 2012, 336, 555 doi: 10.1126/science.1218197
[42]
Sura A, Nehra V. Performance comparison of single level STT and SOT MRAM cells for cache applications. 2021 25th International Symposium on VLSI Design and Test, 2021, 1 doi: 10.1109/VDAT53777.2021.9601129
[43]
Song Y J, Lee J H, Han S H, et al. Demonstration of highly manufacturable STT-MRAM embedded in 28nm logic. 2018 IEEE Int Electron Devices Meet IEDM, 2018, 18.2.1 doi: 10.1109/IEDM.2018.8614635
[44]
JC-14 Quality and reliability of solid state products. Avilable from: https://www. jedec. org/committees/jc-14
[45]
Tsunoda K, Aoki M, Noshiro H, et al. Area dependence of thermal stability factor in perpendicular STT-MRAM analyzed by bi-directional data flipping model. 2014 IEEE International Electron Devices Meeting, 2014, 19.3.1 doi: 10.1109/IEDM.2014.7047082
[46]
Sato H, Yamanouchi M, Ikeda S, et al. Perpendicular-anisotropy CoFeB-MgO magnetic tunnel junctions with a MgO/CoFeB/ Ta/CoFeB/MgO recording structure. Appl Phys Lett, 2012, 101, 022414 doi: 10.1063/1.4736727
[47]
Kim W, Jeong J H, Kim Y, et al. Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node. 2011 Int Electron Devices Meet, 2011, 24.1.1 doi: 10.1109/IEDM.2011.6131602
[48]
Thomas L, Jan G, Zhu J, et al. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications. J Appl Phys, 2014, 115, 172615 doi: 10.1063/1.4870917
[49]
Thomas L, Jan G, Le S, et al. Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method. Appl Phys Lett, 2015, 106, 162402 doi: 10.1063/1.4918682
[50]
Endoh T, Honjo H, Nishioka K, et al. Recent progresses in STT-MRAM and SOT-MRAM for next generation MRAM. IEEE Symposium on VLSI Technology, 2020, 1 doi: 10.1109/VLSITechnology18217.2020.9265042
Fig. 1.  (Color online) SOT device structure and the SOT-MTJs process flow. (a) Three-dimensional schematic pictures of SOT device. (b) Cross-section TEM images cutting along the SOT track (x-direction). (c) Substrate treatment for low roughness. (d) SOT track, MTJ film stack deposition and magnetic anneal. (e) MTJ patterning and encapsulation. (f) Top electrode process.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  (Color online) Detailed microstructure of the MTJ film stack and the resistivity of W. (a) TEM diagram of the MTJ film stack. (b) Nano-beam diffraction analysis of W captured from the red box in (a). EDS mappings of (c) W, (d) Mg, (e) Co and (f) Fe. (g) The XRD curve for a simplified film structure of W/CoFeB/MgO/Ta. (h) The resistivities of W with various thicknesses. The resistivity of 5 nm W is highlighted by red circle. The orange color gradient indicate the W phase transition.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (Color online) The typical electrical and magnetic properties of the SOT device. The wafer level distribution of the RSOT, MR, JSW, RAP and RP. (a) Typical R–H hysteresis loops of the SOT-MTJs. (b) Typical R–J hysteresis loops of the SOT MTJs obtained from the same sample in (a). The wafer-level electrical distribution of (c) RSOT, (d) MR, (e) JSW. (f–h) The corresponding CDF plots. (i) The bit-cell resistance distributions of SOT MTJs for both P and AP states.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Normalized (a) ISW, (b) IFL, (c) ISOT, and (d) IFL/ISW as functions of MTJ long axis b. The data are normalized by the average value of MTJ with b = 2100 nm.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  (Color online) The switching probability (PSW) as a function of applied voltage when pulse widths were varied from 50 µs down to 100 ns for both (a) P-to-AP and (b) AP-to-P directions. (c) The extracted JC at different pulse width for both P-to-AP and AP-to-P directions when PSW = 50%.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  (Color online) (a) RSOT, RP, RAP measured after the corresponding cycling current pulses for a typical SOT-MTJ device. (b) The MR loops were recorded multiple times at each power of 10 pulses up to 1010. (c) The extracted JSW from (b) multiple times at each power of 10 pulses.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  (Color online) (a) The extracted switching probabilities as a function of the external magnetic field and the corresponding fitting curve. (b) Diamond plots of ∆ for the MTJs with various MTJ long axis b. (c) The failure-bit rates of different bake time, i.e., 12, 24, 48 h at 200 °C, respectively.

DownLoad: Full-Size Img PowerPoint
[1]
Dieny B, Prejbeanu I L, Garello K, et al. Opportunities and challenges for spintronics in the microelectronics industry. Nat Electron, 2020, 3, 446 doi: 10.1038/s41928-020-0461-5
[2]
Apalkov D, Dieny B, Slaughter J M. Magnetoresistive random access memory. Proc IEEE, 2016, 104, 1796 doi: 10.1109/JPROC.2016.2590142
[3]
Zhang Y, Zhao W S, Klein J O, et al. Spintronics for low-power computing. 2014 Design, Automation & Test in Europe Conference & Exhibition, 2014, 1 doi: 10.7873/DATE.2014.316
[4]
Chiang H L, Wang J F, Chen T C, et al. Cold MRAM as a density booster for embedded NVM in advanced technology. 2021 Symposium on VLSI Technology, 2021, 1
[5]
Antonyan A, Pyo S, Jung H, et al. Embedded MRAM macro for eFlash replacement. 2018 IEEE International Symposium on Circuits and Systems, 2018, 1 doi: 10.1109/ISCAS.2018.8351201
[6]
Naik V B, Lee K, Yamane K, et al. Manufacturable 22nm FD-SOI embedded MRAM technology for industrial-grade MCU and IOT applications. 2019 IEEE International Electron Devices Meeting, 2019, 2.3.1 doi: 10.1109/IEDM19573.2019.8993454
[7]
Chang L, Fried D M, Hergenrother J, et al. Stable SRAM cell design for the 32 nm node and beyond. 2005 Symposium on VLSI Technology, 2005, 128 doi: 10.1109/.2005.1469239
[8]
Chen Y H, Chan W M, Wu W C, et al. A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. IEEE J Solid-State Circuits, 2015, 50, 170 doi: 10.1109/JSSC.2014.2349977
[9]
Thomas L, Jan G, Serrano-Guisan S, et al. STT-MRAM devices with low damping and moment optimized for LLC applications at Ox nodes. 2018 IEEE Int Electron Devices Meet IEDM, 2018, 27.3.1 doi: 10.1109/IEDM.2018.8614700
[10]
Wang K L, Alzate J G, Amiri P K. Low-power non-volatile spintronic memory: STT-RAM and beyond. J Phys D, 2013, 46, 074003 doi: 10.1088/0022-3727/46/7/074003
[11]
Wang S D, Lee H, Ebrahimi F, et al. Comparative evaluation of spin-transfer-torque and magnetoelectric random access memory. IEEE J Emerg Sel Top Circuits Syst, 2016, 6, 134 doi: 10.1109/JETCAS.2016.2547681
[12]
Endoh T. Nonvolatile logic and memory devices based on spintronics. 2015 IEEE International Symposium on Circuits and Systems, 2015, 13 doi: 10.1109/ISCAS.2015.7168558
[13]
Engel B N, Akerman J, Butcher B, et al. A 4-Mb toggle MRAM based on a novel bit and switching method. IEEE Trans Magn, 2005, 41, 132 doi: 10.1109/TMAG.2004.840847
[14]
Slonczewski J C. Current-driven excitation of magnetic multilayers. J Magn Magn Mater, 1996, 159, L1 doi: 10.1016/0304-8853(96)00062-5
[15]
Huai Y M, Albert F, Nguyen P, et al. Observation of spin-transfer switching in deep submicron-sized and low-resistance magnetic tunnel junctions. Appl Phys Lett, 2004, 84, 3118 doi: 10.1063/1.1707228
[16]
Stiles M D, Zangwill A. Anatomy of spin-transfer torque. Phys Rev B, 2002, 66, 014407 doi: 10.1103/physrevb.66.014407
[17]
Stiles M D, Miltat J. Spin-transfer torque and dynamics. In: Spin Dynamics in Confined Magnetic Structures III. Springer, 2006, 225 doi: 10.1007/10938171_7
[18]
Carboni R, Ambrogio S, Chen W, et al. Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory. 2016 IEEE International Electron Devices Meeting, 2016, 21.6.1 doi: 10.1109/IEDM.2016.7838468
[19]
Li J, Augustine C, Salahuddin S, et al. Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. 2008 45th ACM/IEEE Design Automation Conference, 2008, 278
[20]
Mukhopadhyay S, Mahmoodi H, Roy K. Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans Comput Aided Des Integr Circuits Syst, 2005, 24, 1859 doi: 10.1109/TCAD.2005.852295
[21]
Zhao W S, Zhang Y, Devolder T, et al. Failure and reliability analysis of STT-MRAM. Microelectron Reliab, 2012, 52, 1848 doi: 10.1016/j.microrel.2012.06.035
[22]
Shao Q M, Li P, Liu L Q, et al. Roadmap of spin–orbit torques. IEEE Trans Magn, 2021, 57, 800439 doi: 10.1109/TMAG.2021.3078583
[23]
Guo Z X, Yin J L, Bai Y, et al. Spintronics for energy-efficient computing: An overview and outlook. Proc IEEE, 2021, 109, 1398 doi: 10.1109/JPROC.2021.3084997
[24]
Zhu D Q, Guo Z X, Du A, et al. First demonstration of three terminal MRAM devices with immunity to magnetic fields and 10 ns field free switching by electrical manipulation of exchange bias. 2021 IEEE International Electron Devices Meeting, 2021, 17.5.1 doi: 10.1109/IEDM19574.2021.9720599
[25]
Fukami S, Anekawa T, Zhang C, et al. A spin–orbit torque switching scheme with collinear magnetic easy axis and current configuration. Nat Nanotechnol, 2016, 11, 621 doi: 10.1038/nnano.2016.29
[26]
Honjo H, Nguyen T V A, Watanabe T, et al. First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. 2019 IEEE International Electron Devices Meeting, 2019, 28.5.1 doi: 10.1109/IEDM19573.2019.8993443
[27]
Couet S, Rao S, Van Beek S, et al. BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning. 2021 Symposium on VLSI Technology, 2021, 1
[28]
Rahaman S Z, Wang I J, Wang D Y, et al. Size-dependent switching properties of spin-orbit torque MRAM with manufacturing-friendly 8-inch wafer-level uniformity. IEEE J Electron Devices Soc, 2020, 8, 163 doi: 10.1109/JEDS.2020.2971892
[29]
Lourembam J, Huang L S, Chen B J, et al. Multi-state magnetic tunnel junction programmable by nanosecond spin-orbit torque pulse sequence. Adv Electron Mater, 2021, 7, 2001133 doi: 10.1002/aelm.202001133
[30]
Chen G L, Wang I J, Yeh P S, et al. An 8kb spin-orbit-torque magnetic random-access memory. 2021 International Symposium on VLSI Technology, Systems and Applications, 2021, 1 doi: 10.1109/VLSI-TSA51926.2021.9440096
[31]
Pai C F, Liu L Q, Li Y, et al. Spin transfer torque devices utilizing the giant spin Hall effect of tungsten. Appl Phys Lett, 2012, 101, 122404 doi: 10.1063/1.4753947
[32]
Liu J, Ohkubo T, Mitani S, et al. Correlation between the spin Hall angle and the structural phases of early 5d transition metals. Appl Phys Lett, 2015, 107, 232408 doi: 10.1063/1.4937452
[33]
Embedded Memories Technology scaling & STT-MRAM for IoT & Automotive. IEEE International Electron Devices Meeting Archive, 2017
[34]
Das J, Alam S M, Bhanja S. Non-destructive variability tolerant differential read for non-volatile logic. 2012 IEEE 55th International Midwest Symposium on Circuits and Systems, 2012, 178 doi: 10.1109/MWSCAS.2012.6291986
[35]
Li Z, Yan B N, Yang L, et al. A new self-reference sensing scheme for TLC MRAM. 2015 IEEE International Symposium on Circuits and Systems, 2015, 593 doi: 10.1109/ISCAS.2015.7168703
[36]
Yun J, Nadeau-Dostie B, Keim M, et al. MBIST supported multi step trim for reliable eMRAM sensing. 2020 IEEE International Test Conference, 2020, 1 doi: 10.1109/ITC44778.2020.9325218
[37]
Sun J Z. Spin-current interaction with a monodomain magnetic body: A model study. Phys Rev B, 2000, 62, 570 doi: 10.1103/physrevb.62.570
[38]
Zhu L J, Zhu L J, Shi S J, et al. Enhancing spin-orbit torque by strong interfacial scattering from ultrathin insertion layers. Phys Rev Appl, 2019, 11, 061004 doi: 10.1103/physrevapplied.11.061004
[39]
Lee K, Kang S H. Design consideration of magnetic tunnel junctions for reliable high-temperature operation of STT-MRAM. IEEE Trans Magn, 2010, 46, 1537 doi: 10.1109/TMAG.2010.2043645
[40]
Rahaman S Z, Wang I J, Chen T Y, et al. Pulse-width and temperature effect on the switching behavior of an etch-stop-on-MgO-barrier spin-orbit torque MRAM cell. IEEE Electron Device Lett, 2018, 39, 1306 doi: 10.1109/LED.2018.2856518
[41]
Liu L Q, Pai C F, Li Y, et al. Spin-torque switching with the giant spin Hall effect of tantalum. Science, 2012, 336, 555 doi: 10.1126/science.1218197
[42]
Sura A, Nehra V. Performance comparison of single level STT and SOT MRAM cells for cache applications. 2021 25th International Symposium on VLSI Design and Test, 2021, 1 doi: 10.1109/VDAT53777.2021.9601129
[43]
Song Y J, Lee J H, Han S H, et al. Demonstration of highly manufacturable STT-MRAM embedded in 28nm logic. 2018 IEEE Int Electron Devices Meet IEDM, 2018, 18.2.1 doi: 10.1109/IEDM.2018.8614635
[44]
JC-14 Quality and reliability of solid state products. Avilable from: https://www. jedec. org/committees/jc-14
[45]
Tsunoda K, Aoki M, Noshiro H, et al. Area dependence of thermal stability factor in perpendicular STT-MRAM analyzed by bi-directional data flipping model. 2014 IEEE International Electron Devices Meeting, 2014, 19.3.1 doi: 10.1109/IEDM.2014.7047082
[46]
Sato H, Yamanouchi M, Ikeda S, et al. Perpendicular-anisotropy CoFeB-MgO magnetic tunnel junctions with a MgO/CoFeB/ Ta/CoFeB/MgO recording structure. Appl Phys Lett, 2012, 101, 022414 doi: 10.1063/1.4736727
[47]
Kim W, Jeong J H, Kim Y, et al. Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node. 2011 Int Electron Devices Meet, 2011, 24.1.1 doi: 10.1109/IEDM.2011.6131602
[48]
Thomas L, Jan G, Zhu J, et al. Perpendicular spin transfer torque magnetic random access memories with high spin torque efficiency and thermal stability for embedded applications. J Appl Phys, 2014, 115, 172615 doi: 10.1063/1.4870917
[49]
Thomas L, Jan G, Le S, et al. Quantifying data retention of perpendicular spin-transfer-torque magnetic random access memory chips using an effective thermal stability factor method. Appl Phys Lett, 2015, 106, 162402 doi: 10.1063/1.4918682
[50]
Endoh T, Honjo H, Nishioka K, et al. Recent progresses in STT-MRAM and SOT-MRAM for next generation MRAM. IEEE Symposium on VLSI Technology, 2020, 1 doi: 10.1109/VLSITechnology18217.2020.9265042

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    Received: 25 May 2022 Revised: 27 June 2022 Online: Uncorrected proof: 16 July 2022Published: 01 October 2022

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      Article Navigation >  Journal of Semiconductors  > 2022  >  43(10): 102501
      Hongchao Zhang, Xiangyue Ma, Chuanpeng Jiang, Jialiang Yin, Shuqin Lyu, Shiyang Lu, Xiantao Shang, Bowen Man, Cong Zhang, Dandan Li, Shuhui Li, Wenjing Chen, Hongxi Liu, Gefei Wang, Kaihua Cao, Zhaohao Wang, Weisheng Zhao. Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform[J]. Journal of Semiconductors, 2022, 43(10): 102501. doi: 10.1088/1674-4926/43/10/102501 H C Zhang, X Y Ma, C P Jiang, J L Yin, S Lyu, S Y Lu, X T Shang, B W Man, C Zhang, D D Li, S H Li, W J Chen, H X Liu, G F Wang, K H Cao, Z H Wang, W S Zhao. Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform[J]. J. Semicond, 2022, 43(10): 102501. doi: 10.1088/1674-4926/43/10/102501Export: BibTex EndNote
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      Hongchao Zhang, Xiangyue Ma, Chuanpeng Jiang, Jialiang Yin, Shuqin Lyu, Shiyang Lu, Xiantao Shang, Bowen Man, Cong Zhang, Dandan Li, Shuhui Li, Wenjing Chen, Hongxi Liu, Gefei Wang, Kaihua Cao, Zhaohao Wang, Weisheng Zhao. Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform[J]. Journal of Semiconductors, 2022, 43(10): 102501. doi: 10.1088/1674-4926/43/10/102501

      H C Zhang, X Y Ma, C P Jiang, J L Yin, S Lyu, S Y Lu, X T Shang, B W Man, C Zhang, D D Li, S H Li, W J Chen, H X Liu, G F Wang, K H Cao, Z H Wang, W S Zhao. Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform[J]. J. Semicond, 2022, 43(10): 102501. doi: 10.1088/1674-4926/43/10/102501
      Export: BibTex EndNote
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      Integration of high-performance spin-orbit torque MRAM devices by 200-mm-wafer manufacturing platform

      doi: 10.1088/1674-4926/43/10/102501
      • 1.

        Fert Beijing Institute, School of Integrated Science and Engineering, Beihang University, Beijing 100191, China

      • 2.

        Truth Memory Tech. Corporation, Beijing 100088, China

      • 3.

        Beihang-Goertek Joint Microelectronics Institute, Qingdao Research Institute, Beihang University, Qingdao 266000, China

      More Information
      • Author Bio:

        Hongchao Zhang received the M.S. degree in the school of physics from Qingdao University, Shandong, China, in 2018. He is currently working toward a Ph.D. degree in microelectronics and solid-state electronics at Beihang University, Beijing, China. His current research interests include nanofabrication of magnetic tunnel junctions and the development of SOT MRAM device characteristic techniques

        Hongxi Liu received the Ph.D. degree in Electronics for Informatics from Hokkaido University, Japan, in 2012. He has worked in academia and industry for over 10 years, mainly focusing on the research and development of MRAM technology. He is currently in charge of the activities of SOT MRAM R&D in Truth Memory tech. Corporation, Beijing, China

        Gefei Wang (M’90) received a B.S. degree in electronics and information engineering in 2012 and a M.S. degree in microelectronics and solid-state electronics in 2015 from Beihang University, Beijing, China. From 2015 to 2019, he received Ph.D. degree in physics from Paris-Saclay University, Paris, France. His research interest includes the development of spin-based nano device modeling and spin-based circuit design, especially in memory design

        Kaihua Cao (M’92) received the B.S. degree in microelectronics from Qingdao University, Shandong, China, in 2014 and the Ph.D. degree in microelectronics and solid-state electronics from Beihang University, Beijing, China, in 2019. From 2015 to 2019, he was a joint Ph.D. student with Institute of Microelectronics of The Chinese Academy of Sciences, Beijing, China. His research interest includes the development of STT-MRAM/SOT-MRAM basic cell nanofabrication and characteristic techniques, and fundamental study of processing in memory device

      • Corresponding author: hongxi_liu@tmc-bj.cn; gefei_wang@tmc-bj.cn; kaihua.cao@buaa.edu.cn
      • Received Date: 2022-05-25
      • Revised Date: 2022-06-27
        • Available Online: 2022-07-16

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