J. Semicond. > 2022, Volume 43 > Issue 2 > 023101, doi: 10.1088/1674-4926/43/2/023101

REVIEWS

A review of compact modeling for phase change memory

Feilong Ding1, Baokang Peng1, Xi Li2, Lining Zhang1, , Runsheng Wang3, Zhitang Song2 and Ru Huang3

+ Author Affiliations

 Corresponding author: Lining Zhang, eelnzhang@pku.edu.cn

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Abstract: Phase change memory (PCM) attracts wide attention for the memory-centric computing and neuromorphic computing. For circuit and system designs, PCM compact models are mandatory and their status are reviewed in this work. Macro models and physics-based models have been proposed in different stages of the PCM technology developments. Compact modeling of PCM is indeed more complex than the transistor modeling due to their multi-physics nature including electrical, thermal and phase transition dynamics as well as their interactions. Realizations of the PCM operations including threshold switching, set and reset programming in these models are diverse, which also differs from the perspective of circuit simulations. For the purpose of efficient and reliable designs of the PCM technology, open issues and challenges of the compact modeling are also discussed.

Key words: phase change memory, compact model, macro model, physics-based model



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Fig. 1.  (Color online) Schematics of two typical PCM cell structures: (a) the mushroom type and (b) the confinement type. In between the metal electrodes are the phase change materials, which show the crystalline phase (blue atoms in color) and amorphous phase (silver atoms in color).

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Fig. 2.  (Color online) (a) Stable phase states and the atomistic structures. (b) The phase change dynamics with RESET/SET/READ pulses. Reprinted by permission from Springer Nature Customer Service Centre GmbH: Springer Nature MRS Bulletin, Phase-change materials in electronics and photonics, Wei Zhang et al.[32], 2019.

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Fig. 3.  (Color online) Schematic diagram of the crystallization from the energy perspective. (a) The nucleation is described as a process with energy barrier of Ea1 plus the energy of nucleus ΔG with the critical size rc. (b) The growth is described as a bi-directional process with a barrier of Ea2 and a barrier of |dg|.

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Fig. 4.  Probability densities of nucleation and growth per nanosecond as given by the above CNG model. The bell-shaped characteristics have been widely used in PCM simulations in literature. Reprinted from Ref. [39], with the permission of AIP Publishing.

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Fig. 5.  (Color online) (a) Schematic diagram of three phases and their transitions and (b) dependence of the phase transition rates on temperature. © [2008] IEEE. Reprinted with permission from Ref. [40].

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Fig. 6.  (Color online) Schematic for the memory programing with desired temperature pulses. For a SET there can be two themes: a “solid phase crystallization” (SPC) and a “melting and slow cooling” (MSC). The slow cooling corresponds to a crystallization process below the melting temperature.

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Fig. 7.  (a) Core block of the model. (b) I–V curves from the macro model (line) in comparisons with the experimental data(dots). © [2006] IEEE. Reprinted with permission from Ref. [45].

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Fig. 8.  Flowchart of the binary macro model with different modules to decide the temperature and the phase. © [2006] IEEE. Reprinted with permission from Ref. [46].

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Fig. 9.  I–V characteristics of RESET and SET state, with temperature dependence following the Arrhenius law. The threshold switching is realized by a versatile function F which provides a smooth transition from the high-resistance to low-resistance state. © [2006] IEEE. Reprinted with permission from Ref. [50].

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Fig. 10.  (Color online) Crystallization dynamics as given by the JMAK theory and the experimental data under different temperatures. Temperature dependence of the time constant follows approximately the Arrhenius law. © [2007] IEEE. Reprinted with permission from Ref. [51].

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Fig. 11.  (Color online) Auxiliary circuits are introduced to implement the crystallization kinetics of Eq. (12). © [2007] IEEE. Reprinted with permission from Ref. [51].

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Fig. 12.  (Color online) A dynamic “versatile” function F for descriptions of the threshold switching process in the time domain.

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Fig. 13.  (Color online) (a) Current of the PCM versus voltage with vary amorphization fraction Fa. Dots (experiments), lines (simulations). (b) R–I curve of PCM under different temperature. Dots (experiments), lines (simulations). © [2018] IEEE. Reprinted with permission from Ref. [53].

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Fig. 14.  (Color online) (a) Equivalent circuit model, including all the modules: the transport module, the thermal module and phase transition module. (b) Model compared with experiment data on I–V characteristic. © [2016] IEEE. Reprinted with permission from Ref. [54].

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Fig. 15.  (Color online) (a) The distribution of conductance values as a function of the number of partial SET pulses. Reprinted from Ref. [67], with the permission of AIP Publishing. (b) Modeling the gradual SET process where the crystalline ratio Cf of the PCM is recorded after each pulse.

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Fig. 16.  (Color online) (a) Resistance as a function of time for the amorphous (reset) and crystalline (set) states of a PCM device. © [2010] IEEE. Reprinted with permission from Ref. [72]. (b) Resistance versus time for a reset cell. The two insets represent the mixed-phase structure for relatively short (top left) and long (bottom right) times during the bake experiment. © [2006] IEEE. Reprinted with permission from Ref. [73].

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[1]
Kim T, Lee S. Evolution of phase-change memory for the storage-class memory and beyond. IEEE Trans Electron Devices, 2020, 67, 1394 doi: 10.1109/TED.2020.2964640
[2]
Le Gallo M, Sebastian A. An overview of phase-change memory device physics. J Phys D, 2020, 53, 213002 doi: 10.1088/1361-6463/ab7794
[3]
Gong N B. Multi level cell (MLC) in 3D crosspoint phase change memory array. Sci China Inf Sci, 2021, 64, 1 doi: 10.1007/s11432-021-3184-5
[4]
Lee S H. Technology scaling challenges and opportunities of memory devices. 2016 IEEE International Electron Devices Meeting (IEDM), 2016, 1.1.1 doi: 10.1109/IEDM.2016.7838026
[5]
Kau D, Tang S, Karpov I V, et al. A stackable cross point phase change memory. 2009 IEEE International Electron Devices Meeting, 2009, 1 doi: 10.1109/IEDM.2009.5424263
[6]
https://www.anandtech.com/show/14437/intel-announces-optane-memory-m15-3dxpoint-on-m2-pcie-30-x4
[7]
Arnaud F, Zuliani P, Reynard J P, et al. Truly innovative 28nm FDSOI technology for automotive micro-controller applications embedding 16MB phase change memory. 2018 IEEE International Electron Devices Meeting (IEDM), 2018, 18.4.1 doi: 10.1109/IEDM.2018.8614595
[8]
Cappelletti P, Annunziata R, Arnaud F, et al. Phase change memory for automotive grade embedded NVM applications. J Phys D, 2020, 53, 193002 doi: 10.1088/1361-6463/ab71aa
[9]
https://newsroom.st.com/media-center/press-item.html/p4269.html
[10]
Neale R G, Nelson D L, Moore G E. Nonvolatile and reprogramable, read-mostly memory is here. Electronics, 1970, 43, 56
[11]
Tyson S, Wicker G, Lowrey T, et al. Nonvolatile, high density, high performance phase-change memory. 2000 IEEE Aerospace Conference, 2000, 385 doi: 10.1109/AERO.2000.878512
[12]
Lai S, Lowrey T. OUM – A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications. International Electron Devices Meeting, 2001, 36.5.1 doi: 10.1109/IEDM.2001.979636
[13]
Oh J H, Park J H, Lim Y S, et al. Full integration of highly manufacturable 512Mb PRAM based on 90nm technology. 2006 International Electron Devices Meeting, 2006, 1 doi: 10.1109/IEDM.2006.346905
[14]
Annunziata R, Zuliani P, Borghi M, et al. Phase change memory technology for embedded non volatile memory applications for 90nm and beyond. 2009 IEEE International Electron Devices Meeting, 2009, 1 doi: 10.1109/IEDM.2009.5424413
[15]
Im D H, Lee J I, Cho S L, et al. A unified 7.5nm dash-type confined cell for high performance PRAM device. 2008 IEEE International Electron Devices Meeting, 2008, 1 doi: 10.1109/IEDM.2008.4796654
[16]
Kim T, Choi H, Kim M, et al. High-performance, cost-effective 2z nm two-deck cross-point memory integrated by self-align scheme for 128 Gb SCM. 2018 IEEE International Electron Devices Meeting, 2018, 37.1.1 doi: 10.1109/IEDM.2018.8614680
[17]
Chien W C, Ho Y H, Cheng H Y, et al. A novel self-converging write scheme for 2-bits/cell phase change memory for storage class memory (SCM) application. 2015 Symposium on VLSI Technology, 2015, T100 doi: 10.1109/VLSIT.2015.7223709
[18]
Gong N, Idé T, Kim S, et al. Signal and noise extraction from analog memory elements for neuromorphic computing. Nat Commun, 2018, 9, 2102 doi: 10.1038/s41467-018-04485-1
[19]
Kim S, Ishii M, Lewis S, et al. NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in situ learning. 2015 IEEE International Electron Devices Meeting, 2015, 17.1.1 doi: 10.1109/IEDM.2015.7409716
[20]
Bedeschi F, Fackenthal R, Resta C, et al. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE J Solid State Circuits, 2009, 44, 217 doi: 10.1109/JSSC.2008.2006439
[21]
Suri M N, Bichler O, Querlioz D, et al. Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction. 2011 International Electron Devices Meeting, 2011, 4.4.1 doi: 10.1109/IEDM.2011.6131488
[22]
Suri M N, Bichler O, Querlioz D, et al. Physical aspects of low power synapses based on phase change memory devices. J Appl Phys, 2012, 112, 054904 doi: 10.1063/1.4749411
[23]
Tuma T, Pantazi A, Le Gallo M, et al. Stochastic phase-change neurons. Nat Nanotechnol, 2016, 11, 693 doi: 10.1038/nnano.2016.70
[24]
Wright C D, Hosseini P, Diosdado J A V. Beyond von-Neumann computing with nanoscale phase-change memory devices. Adv Funct Mater, 2013, 23, 2248 doi: 10.1002/adfm.201202383
[25]
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    Received: 24 August 2021 Revised: 16 October 2021 Online: Accepted Manuscript: 21 December 2021Uncorrected proof: 26 January 2022Published: 01 February 2022

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      Article Navigation >  Journal of Semiconductors  > 2022  >  43(2): 023101
      Feilong Ding, Baokang Peng, Xi Li, Lining Zhang, Runsheng Wang, Zhitang Song, Ru Huang. A review of compact modeling for phase change memory[J]. Journal of Semiconductors, 2022, 43(2): 023101. doi: 10.1088/1674-4926/43/2/023101 F L Ding, B K Peng, X Li, L N Zhang, R S Wang, Z T Song, R Huang, A review of compact modeling for phase change memory[J]. J. Semicond., 2022, 43(2): 023101. doi: 10.1088/1674-4926/43/2/023101.Export: BibTex EndNote
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      Feilong Ding, Baokang Peng, Xi Li, Lining Zhang, Runsheng Wang, Zhitang Song, Ru Huang. A review of compact modeling for phase change memory[J]. Journal of Semiconductors, 2022, 43(2): 023101. doi: 10.1088/1674-4926/43/2/023101

      F L Ding, B K Peng, X Li, L N Zhang, R S Wang, Z T Song, R Huang, A review of compact modeling for phase change memory[J]. J. Semicond., 2022, 43(2): 023101. doi: 10.1088/1674-4926/43/2/023101.
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      A review of compact modeling for phase change memory

      doi: 10.1088/1674-4926/43/2/023101
      • 1.

        School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China

      • 2.

        Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China

      • 3.

        Institute of Microelectronics, Peking University, Beijing 100871, China

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      • Author Bio:

        Feilong Ding is currently pursuing a master's degree with Peking University, China. His research interests include phase change memory modeling and simulation

        Baokang Peng received a BS degree in Electronic Science and Technology, in 2021, from Xidian University, Xian,China. He is currently working toward a PhD degree in microelectronics and solid state electronics at PekingUniversity. His research interests include modeling and simulation of semiconductor devices

        Lining Zhang is an assistant professor with Peking University Shenzhen. He is currently a senior member of IEEE,and a member of IEEE EDS Technical Committee (Compact Modeling). His research interests include semiconductor device physics, compact modeling, circuit simulation algorithm and neuromorphic computing

      • Corresponding author: eelnzhang@pku.edu.cn
      • Received Date: 2021-08-24
      • Revised Date: 2021-10-16
      • Published Date: 2022-02-10

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