REVIEWS

Trending IC design directions in 2022

Chi-Hang Chan1, Lin Cheng2, Wei Deng3, Peng Feng4, Li Geng5, Mo Huang1, Haikun Jia3, Lu Jie3, Ka-Meng Lei1, Xihao Liu5, Xun Liu6, Yongpan Liu3, Yan Lu1, , Kaiming Nie7, Dongfang Pan2, Nan Qi4, Sai-Weng Sin1, Nan Sun3, Wenyu Sun3, Jiangtao Xu7, Jinshan Yue3, Milin Zhang3 and Zhao Zhang4

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 Corresponding author: Yan Lu, yanlu@um.edu.mo

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Abstract: For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

Key words: integrated circuit designartificial intelligence (AI)radio frequency (RF) circuitsdata converterspower managementimagersensorcryogenicbiomedical



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Fig. 1.  (Color online) Comparison of the state-of-the-art CIM macros (scaled to 4-bit input, 4-bit weight), with (a) energy efficiency and area efficiency, and (b) performance and storage capacity.

Fig. 2.  (Color online) Trends of the number of CA from downlink path and maximum BW per path for recent cellular SoC implementations.

Fig. 3.  (Color online) Trends of wireline communication circuits: power efficiency and data rate.

Fig. 4.  (Color online) The jitter variance versus power of the recently published PLLs from ISSCC/JSSC.

Fig. 5.  Simplified PLL linear phase noise model with its noise transfer function of the PD.

Fig. 6.  (Color online) The state-of-the-art PA peak PAE and Psat performance in different processes[90].

Fig. 7.  (Color online) The state-of-the-art oscillator FoM and FoMT at 1MHz offset versus frequency.

Fig. 8.  (Color online) The trends of (a) startup time and (b) startup energy of the MHz-range fast startup XO.

Fig. 9.  (Color online) Comparison between NS-SAR and conventional architectures.

Fig. 10.  (Color online) Schreier figure-of-merit (FoMs) and bandwidth (BW) of NS-SAR over years.

Fig. 11.  (Color online) (a) The basic framework of NS-SAR, and (b) its signal model.

Fig. 12.  (Color online) Block diagram of DT-Slicing IADC in Ref. [150].

Fig. 13.  (Color online) Block diagram of DT Linear-Exponential IADC in Ref. [152].

Fig. 14.  (Color online) Block diagram of DT-Zoom IADC in Ref. [155].

Fig. 15.  (Color online) Block diagram of CT IADC in Ref. [157].

Fig. 16.  (Color online) State-of-the-art Nyquist ADCs survey published in ISSCC and VLSI[123, 161].

Fig. 17.  Early pipelined ADC patent with 1 b/stage[162].

Fig. 18.  (Color online) ADC survey with Schreier FoM vs. speed.

Fig. 19.  (Color online) ADC survey with energy vs. SNDR.

Fig. 20.  Overview map of hybrid DC–DC topologies and their relevance.

Fig. 21.  (Color online) Block diagram of an isolated DC–DC converter.

Fig. 22.  (Color online) Peak efficiency, maximum output power and EMI performance comparison for the reported isolated DC–DC converters.

Fig. 23.  Design directions of supply modulators.

Fig. 24.  (Color online) Comparison of state-of-the-art supply modulators showing efficiency versus bandwidth.

Fig. 25.  (a) DVS Pixel circuit diagram[239]. (b) Pixel-triggered event process.

Fig. 26.  (Color online) The evolution of the event sensor process.

Fig. 27.  (Color online) Pixel size and event rate of the event sensors.

Fig. 28.  (Color online) Summary of high dynamic range techniques.

Fig. 29.  (Color online) Principles of ToF sensor system.

Fig. 30.  (Color online) Number of pixels versus the maximum detection distance of ToF sensors.

Table 1.   Performance summary of AI chips for different DSA.

Speech
(KWS/ASR)
ISSCC’20,
14.1, [1]
ISSCC’21,
9.9, [2]
ISSCC’21,
9.8, [3]
Technology (nm)28 90 16
ModelDSCNNDTRNN
Memory2 KB9.8 MB
Latency (ms)64 <100 15–45
Power (μW)0.51 6 1.11 × 105
Word1–2 1 2 × 105
DenoisingNoYesYes
Speech
(VAD)
ISSCC’19,
17.2, [4]
ISSCC’22,
22.5, [5]
Technology (nm)180 28
Feature typeMixed-signalTD-CNN
Channel number16–4860
Freq. range (Hz)75–4000 100–4000
VAD power (nW)142 108
VAD accuracy90% @ nonspeech94% @ nonspeech
Energy/
Classification (nJ)
73 1.08
Image/VideoISSCC’21,
9.7, [6]
ISSCC’22,
33.4, [7]
ISSCC’20,
14.2, [8]
Technology (nm)65 65 65
ModelEdge CNN
(GTR)
Point CNN
(3D detection)
MobileNet
(Classification)
Memory (KB)364 KB196 KB
Power (mW)0.184 544–6097.3–99
Frame
efficiency
30 fps3.2 mJ/Frame24.7–183.2 μJ/Frame
Emerging directionsISSCC’22,
29.2, [9]
ISSCC’22,
29.3, [10]
Technology (nm)28 28
App.TransformerTransformer
Memory (KB)336 192
Energy
efficiency (TOPS/W)
1.91–27.56
5.1–20.5
Power (mW)12–272 27–118
DownLoad: CSV

Table 2.   Summary of the SRAM-based CIM macros.

Ref.CIM modeTech. (nm)Macro sizeInput precision (bit)Weight precision (bit)Output ratioPerformance (TOPS)Energy efficiency (TOPS/W)Area
efficiency (TOPS/mm2)
Inference accuracy (Cifar-10)
[13],
2020
Current
based
28 64 Kb4/84/81 : 168.44@4b/4b
16.63@8b/8b
92.02%
[14],
2020
65 16 Kb2/4/6/84/81 : 122.0*@2b/4b158.7*@2b/4b3.38*@2b/4b91.74%
[15],
2021
65 64 Kb2/4/6/81−81 : 13.16*@2b/1b370*@2b/1b1.85*@2b/1b92.65%
[22],
2021
Charge
based
28 384 Kb4/84/81 : 194.31@4b/4b
[23],
2021
16 4.5 Mb1−81−81 : 4.511.8@4b/4b121@4b/4b2.67@4b/4b91.51%
[16],
2021
All- digital22 64 Kb1−84/8/12/161 : 13.3@4b/4b89*@4b/4b16.3*@4b/4b#
[17],
2022
28 32 Kb1−81/4/81 : 127.38@8b/8b#
[20],
2022
5 64 Kb441 : 12.94@4b/4b254*@4b/4b221@4b/4b#
[21],
2022
28 16 Kb111 : 120@1b/1b2219@1b/1b606@1b/1b86.9%
[18],
2022
Time
based
28 1 Mb4/84/81 : 14.96@4b/4b148.1*@4b/4b
37.01*@8b/8b
92.08%
*: with sparsity improvement or at 10% input toggle rate. @4b/4b: 4bit input, 4bit weight. #: the same accuracy to the software baseline at the same precision.
DownLoad: CSV

Table 3.   Performance comparison of IADCs.

P. VogelmannS. MohammadB. WangY. LiuL. JieM. MokhtarM. Mokhtar
ISSCC'18, JSSC'19,
[150]
JSSC'20,
[151]
VLSI'18, JSSC'19,
[152]
ISSCC'22,
[155]
ISSCC'22,
[156]
ESSCIRC'19, SSCL'19,
[157]
CICC'21,
[159]
ArchitectureDT SlicingDT IADC+SAR, cap scalingDT Linear-ExpDT ZoomCT-Zoom-CountingCTCTI-SMASH
Tech. (nm)18018065552818028
Supply (V)31.81.211.230.9
Active area (mm2)0.3630.660.130.230.0140.1750.125
OSR15098256128819216060
Bandwidth (kHz)1002.04201.35251001000
Power (μW)109825.45504.9659012703600
SNDR (dB)86.695.5100.893*100.18381.2
SFDR (dB)101.3106121N/A113.794.397
FoMS (SNDR)166.2175176.4177.3*176.4161.9165.6
* Only SNR is available for FoMS calculation.
DownLoad: CSV

Table 4.   Pros and cons of different hybrid DC–DC topologies.

FCMLHybrid SCInductor-firstDual-pathDSD
Typical topology
ProsSmall IL ripple
Wide VCR range
Small IL ripple
Wide VCR range
Small IL & ripple Continuous IIN
Small IL & ripple
High power density
Small IL ripple
Shared IL
Less components
ConsNeeds CF balancing Large ILNeeds CF balancing
Large IL
Many components
Extra L
Limited VCR range Negative voltage
Hard charging
Limited VCR range
Extra inductor
Needs 1 HV device
DownLoad: CSV

Table 5.   Recent fast-transient DC–DC converters.

[208][209][210][211][212][213][214][215][206]
Process (nm)13018018028350284180 BCD180 BCD
TopologyBuckBuckBuckBuckBuckBuckBuckDSDCCC
Vin (V)3.33.33−51.23.31.21.812/2412
Vout (V)1.81−2.50.5−2.50.6−10.3−2.60.45−0.9110.9−1.8
fsw (MHz)30103075254005012
Phase number114446422
Inductor/phase (nH)90200100152001 (bond-wire)5 (in package)1800740
Cout (μF)0.9420.840.22.470.00020.81010.6
Control law & transient techniqueVM & LDO assistSH & DABVM & OCBDAOTSH & AW, APCVMVMVM & delay-insensitive, DP chargingSH & Intrinsic
DP charging
Auto phase sheddingn.a.n.a.NoYesYesYesYesn.a.n.a.
Compensator optimizationn.a.n.a.NoNot necessaryNot necessaryYesYesn.a.n.a.
Peak efficiency90.70%91%91%89%@1 V88.10%83.70%91.50%88.3%@1 V86.8%@1.2 V
Iload (A)1.25121411034
t (ns)2351051102020
Vout (V)0.0360.0310.0340.080.10.20.090.0560.11
Normalized ∆Vout0.7421.0821.00812.8001.096n.a.*2.5603.8334.981
*Load current step edge time ∆t is too slow that is comparable to its switching cycle.
DownLoad: CSV

Table 6.   Performance summary of state-of-the-art event sensors.

SupplierIniVationPropheseeSamsungCelePixel
Journal, Year, RefJSSC, 2008,
[239]
JSSC, 2014,
[246]
JSSC, 2015,
[240]
VLSI, 2019,
[244]
JSSC, 2011,
[247]
ISSCC, 2020,
[242]
ISSCC, 2017,
[241]
ISCAS, 2020,
[243]
CVPR, 2019,
[248]
Resolution (pixel)128 × 128240 × 18060 × 30132 × 104304 × 2401280 × 720640 × 4801280 × 9601280 × 800
Latency (µs)1212N/AN/A320–15065–410150N/A
DR (dB)120120130N/A143> 12490100N/A
Sensitivity (%)17111N/A1311920N/A
Power (mW)235–140.724.950–17532–8427–50130400
Chip size (mm2)6.3 × 65 × 53.2 × 1.62 × 29.9 × 8.26.22 × 3.58 × 5.88.4 × 7.62 × 2
Pixel size (µm2)40 × 4018.5 × 18.531.2 × 31.210 × 1030 × 304.86 × 4.869 × 94.95 × 4.959.8 × 9.8
Fill factor (%)8.12210.32020> 771122N/A
Max event rate (Meps)112N/A180N/A10663001300N/A
Stationary noise
(ev/pix/s)
0.050.1N/AN/A0.10.03N/AN/A
Technology (nm)350
FSI
180
FSI
180
FSI
65 FSI180
FSI
90
BSI-stacked
90
BSI
65
BSI-stacked
65
FSI
Grayscale outputnoyesnonoyesnononoyes
Grayscale DR (dB)N/A55N/AN/A130N/AN/AN/AN/A
Max. frame rate (fps)N/A35N/AN/AN/AN/AN/AN/AN/A
DownLoad: CSV

Table 7.   Performance summary of the state-of-the-art HDR sensors.

IEDM, 2019,
[250]
IISW, 2020,
[251]
ISCAS, 2020,
[254]
ISSCC, 2020,
[255]
EDL, 2020,
[256]
JSSC, 2018,
[258]
VLSI, 2021,
[259]
Sensor typeMulti-gain responseMulti-gain responseNon-linear responseNon-linear responseLow-noiseLow-noiseQIS
ProcessN/A45 nm CIS/
65 nm logic
350 nm CIS90 nm CIS/
45 nm logic
180 nm CIS45 nm CIS/
65 nm Logic
45 nm CIS/
65 nm Logic
Pixel array64 M0.8 M0.07 M9.2 M0.02 M8.3 M4 M
Pixel pitch (μm)N/A4154.86NA1.12.2
FWC (e-)1.2 × 1041.3 × 105N/AN/A6.5 × 103N/A3 × 104
Noise (e-)1.24N/AN/A0.320.660.27
DR (dB)8090124>124 dB84.8N/A100
DownLoad: CSV

Table 8.   Performance summary of the state-of-the-art ToF sensors.

ISSCC ‘22, Canon,
[260]
ISSCC ‘21, Neuchâtel,
[261]
ISSCC ‘21, Sony,
[262]
ISSCC ‘20, Sungkyunkwan
U., [265]
JSSC ‘21, Samsung,
[266]
ISSCC ‘2, Panasonic,
[271]
ISSCC ‘22,
UNIST,
[272]
ToF typeDirectDirectDirectIndirectIndirectDirect+IndirectDirect+Indirect
Process90 nm/40 nm
3D-BSI CMOS
45 nm CIS
3D-BSI
90 nm/40 nm
3D BSI CMOS
90 nm
BSI CMOS
65 nm/65 nm
3D BSI CMOS
65 nm
CMOS
110 nm
Pixel array960 × 960256 × 128189 × 600320 × 2401280 × 9601200 × 90080 × 60
Pixel pitch (μm)9.58571083.5675
Wavelength (nm)510780905N/A850/940N/A905
Fill factor (%)~100N/AN/A43N/AN/A10.4
Frame rate (fps)90N/A2010−606045030
Maximum range (m)N/A100 150−200 0.75–4.0 0.4–4.0 250 45
Depth resolution/
Depth noise
N/A7 cm15–30 cm<0.54%<0.92% (full)
<0.3% (2 × 2 bin)
1.5 m@max.range
10 cm@min.range
2.5 cm
DR (dB)143N/AN/AN/AN/AN/AN/A
Background light (klux)N/A8–10117 >120 0.7/20N/A30
Power (mW)330–37051.9N/AN/A290 (full),
220 (2 × 2 bin)
25001500
DownLoad: CSV
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    Received: 30 March 2022 Revised: 23 April 2022 Online: Accepted Manuscript: 01 May 2022Uncorrected proof: 06 May 2022Published: 01 July 2022

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      Chi-Hang Chan, Lin Cheng, Wei Deng, Peng Feng, Li Geng, Mo Huang, Haikun Jia, Lu Jie, Ka-Meng Lei, Xihao Liu, Xun Liu, Yongpan Liu, Yan Lu, Kaiming Nie, Dongfang Pan, Nan Qi, Sai-Weng Sin, Nan Sun, Wenyu Sun, Jiangtao Xu, Jinshan Yue, Milin Zhang, Zhao Zhang. Trending IC design directions in 2022[J]. Journal of Semiconductors, 2022, 43(7): 071401. doi: 10.1088/1674-4926/43/7/071401 C H Chan, L Cheng, W Deng, P Feng, L Geng, M Huang, H K Jia, L Jie, K M Lei, X H Liu, X Liu, Y P Liu, Y Lu, K M Nie, D F Pan, N Qi, S W Sin, N Sun, W Y Sun, J T Xu, J S Yue, M L Zhang, Z Zhang. Trending IC design directions in 2022[J]. J. Semicond, 2022, 43(7): 071401. doi: 10.1088/1674-4926/43/7/071401Export: BibTex EndNote
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      Chi-Hang Chan, Lin Cheng, Wei Deng, Peng Feng, Li Geng, Mo Huang, Haikun Jia, Lu Jie, Ka-Meng Lei, Xihao Liu, Xun Liu, Yongpan Liu, Yan Lu, Kaiming Nie, Dongfang Pan, Nan Qi, Sai-Weng Sin, Nan Sun, Wenyu Sun, Jiangtao Xu, Jinshan Yue, Milin Zhang, Zhao Zhang. Trending IC design directions in 2022[J]. Journal of Semiconductors, 2022, 43(7): 071401. doi: 10.1088/1674-4926/43/7/071401

      C H Chan, L Cheng, W Deng, P Feng, L Geng, M Huang, H K Jia, L Jie, K M Lei, X H Liu, X Liu, Y P Liu, Y Lu, K M Nie, D F Pan, N Qi, S W Sin, N Sun, W Y Sun, J T Xu, J S Yue, M L Zhang, Z Zhang. Trending IC design directions in 2022[J]. J. Semicond, 2022, 43(7): 071401. doi: 10.1088/1674-4926/43/7/071401
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      Trending IC design directions in 2022

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        Chi-Hang Chan was born in Macau S.A.R., China, in 1985. He received the B.S. degree in electrical engineering from University of Washington (U.W. Seattle), USA, in 2008, the M.S. and Ph.D. degree from the University of Macau, Macao, China, in 2012 and 2015, respectively, where he currently serves as an Assistant Professor. He is the recipient of the 2015 IEEE Solid-State-Circuit-Society (SSCS) Pre-doctoral Achievement Award. He also is the co-recipient of the 2014 ESSCIRC best paper award. His research interests include Nyquist and oversampling ADCs, PLL, hardware security and mixed-signal circuits

        Lin Cheng received the B.Eng degree from Hefei University of Technology, Hefei, in 2008, the M.Sc. degree from Fudan University, Shanghai, in 2011, and the Ph.D. degree from The Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in 2016. In 2018, he joined the School of Microelectronics, USTC, where he is currently a Professor. Before that, he was a Post-doc Researcher with HKUST and an Analog Design Intern with Broadcom, San Jose, USA. His current research interests include power management and mixed-signal integrated ICs, wireless power transfer circuits and systems, and automotive ICs. Dr. Cheng was a recipient of the IEEE SSCS Pre-doctoral Achievement Award 2014–2015, Hong Kong Institution of Science 2018 Young Scientist Awards (Honorable Mention)

        Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, and the Ph.D. degree from the Tokyo Institute of Technology, Japan. He was with Apple Inc., Cupertino, CA, USA and currently he is an Associate Professor at Tsinghua University. He is a TPC Member of ISSCC, VLSI, and ESSCIRC. He is an AE of the IEEE SSC-L

        Peng Feng got his BS degree in 2006 at Sichuan University and the PhD degree in 2011 at the Institute of Semiconductors, Chinese Academy of Sciences (CAS). He is now an associate researcher at the Institute of Semiconductors, CAS. His research interests include ultra-low power mixed signal/RF integrated circuits and CMOS image sensors

        Li Geng is currently a Professor with the School of Microelectronics, Xi’an Jiaotong University, Xi’an. Her research interests include power management integrated circuits, low-voltage low-power analog and mixed-signal integrated circuits, RF integrated circuit, and bio-implant systems. Dr. Geng was a Technical Program Committee Member of ASSCC from 2010 to 2018. She is currently a Technical Program Committee Member of ISSCC. She was a recipient of the Science and Technology Improvement Award by the Ministry of National Mechanical Industry, China, in 1999, and also the Science and Technology Improvement Award by Shaanxi Municipal Government in 2000, 2001, 2010, 2015 and 2021

        Mo Huang received the B.Sc., M.Sc., and Ph.D. degrees in microelectronics and solid-state electronics from Sun Yat-sen University, Guangzhou, China, in 2005, 2008, and 2014, respectively. From 2008 to 2014, he was an IC Design Engineer and a Project Manager with Rising Microelectronic Ltd., Guangzhou, China. From 2015 to 2016, he was a Post-Doctoral Fellow with the State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China. From 2017 to 2019, he was with the School of Electronic and Information Engineering, South China University of Technology, Guangzhou, China, as an Associate Professor. He is now an Assistant Professor with Institute of Microelectronics, University of Macau, Macau, China. His current research interests include power management IC design

        Haikun Jia received the Ph.D. and B.S. degree in electronics engineering from Tsinghua University, Beijing, China, in 2015 and 2009, respectively. Since 2020, He works as an Assistant Professor in Tsinghua University. His research interests include millimeter-wave integrated circuits, systems, and high-speed wireline transceivers

        Lu Jie received the B.Eng. degree in Electrical and Electronic Engineering from the Zhejiang University, Hangzhou, Zhejiang, China, in 2017, M.S. and Ph.D. degree in Electrical and Computer Engineering from the University of Michigan, Ann Arbor, US, in 2021. Since 2021, he is currently with Tsinghua University, Beijing, China, as an Assistant Professor. His research interest includes hybrid-architecture ADCs, high-speed circuits, and mixed-signal computation

        Ka-Meng Lei received the B.Sc. degree in EEE from the University of Macau in 2012. He received the Ph.D. degree in ECE in the State-Key Laboratory of AMS-VLSI and FST, University of Macau, in 2016. He serves as an Assistant Professor at the University of Macau since 2019. He was a Postdoctoral Fellow at Harvard University from 2017 to 2019. His current research interests include ultralow voltage analog circuit techniques, sensors and analog front-end interfaces, and high-resolution portable NMR platform. Dr. Lei (co-)received Distinguished Design Award in IEEE A-SSCC 2015; the Silkroad Award in ISSCC 2016; and IEEE SSCS Pre-doctoral Achievement Award 2017. He serves as the TPC member of ICTA. He is the Associate Editor of IEEE Open Journal of Circuits and Systems

        Xihao Liu received the B.Sc. degree in microelectronics from Xi’an Jiaotong University, Xi’an, China, in 2020, where he is currently working toward the Ph.D. degree in the School of Microelectronics. His research interests include power management circuit and system design

        Xun Liu is an Assistant Professor with the School of Science and Engineering (SSE), Chinese University of Hong Kong, Shenzhen. She received the B.Eng. degree in Electronic and Information Engineering from Zhejiang University, China in 2011, and the Ph.D. degree in electronic and computer engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2017. She was a senior design engineer with Qualcomm, Santa Clara, USA, working on cutting-edge integrated circuits and systems designs for 5G application, and holding 2 US patents. She is a TPC Member of ISSCC

        Yongpan Liu received the B.S. (99), M.S. (02), and Ph.D. (07) degrees all from Tsinghua University. He is currently a Full Professor (Cheung Kong Scholar) with the Department of Electronic Engineering, Tsinghua University, China. Prof. Liu is a Program Committee Member for ISSCC, A-SSCC and DAC. He served as General Secretary for ASPDAC 2021 and Technical Program Chair for NVMSA 2019. He was Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the IEEE Transaction on Circuits and Systems II, and the IET Cyber-Physical Systems. He is an IEEE Senior Member. He served as A-SSCC 2020 and AICAS 2022 tutorial speaker and IEEE CASS Distinguished Lecturer 2021

        Yan Lu received his BEng and MSc degrees from South China University of Technology, Guangzhou, in 2006 and 2009, respectively, and the PhD degree in 2013 from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China. In 2014, he joined the State Key Laboratory of AMS-VLSI, University of Macau, Macao, China, where he is currently an Associate Professor. He has authored/coauthored two books and more than 120 peer-reviewed technical papers. His research interests include wireless power transfer circuits and systems, high density power converters, integrated voltage regulators. He served as a Guest Editor for IEEE JSSC, TCAS-I and TCAS-II, is serving on the TPC of ISSCC and CICC, and is an IEEE SSCS Distinguished Lecturer 2022-23

        Kaiming Nie received the B.E., M.S., and Ph.D. degrees from the School of Electronic Information and Engineering, Tianjin University, Tianjin, China, in 2009, 2011, and 2014, respectively. From July 2014 to September 2017, he had been a post-doctoral researcher at the same institution. Since September 2017, he has been an Associate Professor at the School of Microelectronics, Tianjin University. His research interests are in mixed analog/digital circuit design and CMOS image sensor design

        Dongfang Pan received the Ph.D. degree in electronics science and technology from the Department of Electronics Science and Technology, University of Science and Technology of China (USTC), China, in 2019. From 2018 to 2019, He was a Visiting Scholar with the Department of Electrical Engineering, Southern Methodist University (SMU), Dallas, USA. From 2019 to 2021, he was a Post-Doctoral Fellow with the School of Microelectronics, USTC. He is currently an Associate Researcher with the School of Microelectronics at USTC. His research interests include Isolated DC-DC converters, high-frequency power ICs, CMOS RF transceivers, and system designs including PA, LNA, VCO, and analog IC

        Nan Qi received the B.S. degree from Beijing Institute of Technology, Beijing, China, in 2005, the M.S. and Ph.D. degrees in microelectronics from Tsinghua University, Beijing, in 2008 and 2013, respectively. From 2013 to 2015, he was a Research Scholar with the Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA. From 2015 to 2017, he was a Visiting Scholar and Circuit-Design Engineer at Hewlett-Packard Labs, Palo Alto, CA, USA. In 2017, he joined the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, where he is now a Professor of Electrical Circuits and Systems. His research interests include the design of integrated circuits for high-speed wireline and optical transceivers

        Sai-Weng Sin is currently an Associate Professor with the Dept. of ECE, Faculty of Science and Technology, and the Deputy Director of State-Key Laboratory of AMS-VLSI, University of Macau. He holds 7 US and 3 Taiwan patents and 150 technical journals and conference papers in the field of high-performance data converters and analog mixed-signal integrated circuits. Dr. Sin is a TPC member of IEEE A-SSCC. He served as an Associate Editor for the IEEE Transaction on Circuits and Systems II – Express Briefs. He was the co-recipient of the 2011 ISSCC Silk Road Award, Student Design Contest Award in A-SSCC 2011 and the 2011 State Science and Technology Progress Award (second-class), China

        Nan Sun is a Professor with Tsinghua University since 2020. He was Assistant and then tenured Associate Professor with University of Texas at Austin. He received B.S. degree from Tsinghua University in 2006, and Ph.D. degree from Harvard University in 2010. Dr. Sun received the NSF Career Award in 2013, and the IEEE SSCS New Frontier Award in 2020. He has published 30+ JSSC papers and 50+ ISSCC/VLSI/CICC/ESSCIRC papers. He has graduated 26 PhD students, 10 of whom are professors at top universities in the US and China. He serves on the TPC of ISSCC, CICC, and ASSCC. He was Associate Editor of IEEE TCAS-I, and a Guest Editor of JSSC. He also serves as Distinguished Lecturer for both IEEE Circuits-and-Systems Society and IEEE Solid-State Circuits Society

        Wenyu Sun received B.S. degree and Ph.D. degree in electrical engineering from Tsinghua University, Beijing, China, in 2016 and 2021, respectively. He is currently a post-doctoral researcher at Tsinghua Shenzhen International Graduate School. His research interests include deep learning and energy-efficient circuit design for AI accelerators, and he has authored or co-authored more than 15 papers in related conferences and transactions. He won the second place in EDAthon 2017 (Programming Competition on Electronic Design Automation) hosted by IEEE CEDA, and the second prize of final contest in International Invitational Tournament for Brain-inspired Computing and Application 2017

        Jiangtao Xu received the B.E., M.S., and Ph.D. degrees from the School of Electronic Information and Engineering, Tianjin University, Tianjin, China, in 2001, 2004, and 2007, respectively. From 2007 to 2010, he was a Lecturer, and from 2010 to 2018 he was an Associate Professor at Tianjin University. Since 2018, he has been a professor at the School of Microelectronics, Tianjin University. His research interests are in CMOS image sensors and mixed signal integrated circuits

        Jinshan Yue received the B.S. and Ph.D. degree from the Electronic Engineering Department, Tsinghua University, Beijing, China, in 2016 and 2021, respectively. He is currently a post doctor and research assistant in the Institute of Microelectronics, Chinese Academy of Sciences. His current research interests include energy-efficient neural network processor, non-volatile memory, and computing-in-memory system design. He has authored and co-authored over 30 technical papers. He has received the excellent doctoral dissertation of Tsinghua University, ASP-DAC2021 Student Research Forum Best Poster Award, and 2021 Beijing Nova Program

        Milin Zhang is an Associate Professor in the Department of Electronic Engineering, Tsinghua University. She received the B.S. and M.S. degrees in electronic engineering from Tsinghua University, Beijing, China, in 2004 and 2006, respectively, and the Ph.D. degree in the ECE Department, Hong Kong University of Science and Technology (HKUST), Hong Kong. Then, she worked as a postdoctoral researcher at the University of Pennsylvania, USA. She joined Tsinghua University in 2016. Her research interests include designing of various non-traditional imaging sensors and biomedical sensing applications. She serves and has served as the TPC member of ISSCC, CICC, A-SSCC and ISCAS. She is the Chapter Chair of the SSCS Beijing chapter

        Zhao Zhang received the Ph.D. degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, in 2016. From 2016 to 2018, he was a Post-Doctoral Fellow with The Hong Kong University of Science and Technology, Hong Kong. From 2019 to 2020, he was an Assistant Professor with Hiroshima University, Higashi-Hiroshima, Japan. In 2020, he joined the Institute of Semiconductors, Chinese Academy of Sciences, where he is currently a Full Professor. His research interests include the design of low-jitter PLLs, ultra-high-speed wireline transceivers, and ultra-low-voltage ICs. He (co)authored more than 40 conference and journal papers, including ISSCC, VLSI and JSSC. He is the guest editor of Electronics Letters, and a reviewer of JSSC, TCAS-I, TCAS-II, TMTT

      • Corresponding author: yanlu@um.edu.mo
      • Received Date: 2022-03-30
      • Revised Date: 2022-04-23
      • Available Online: 2022-05-01

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