Fig. 1.
(Color online) The CMOS circuit configuration that is used in this work
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| Citation: |
Tongtong Yang, Yan Wang, Ruifeng Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. Journal of Semiconductors, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801
T T Yang, Y Wang, R F Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. J. Semicond, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801
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Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique
doi: 10.1088/1674-4926/43/8/082801
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Abstract
In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.-
Keywords:
- SiC,
- CMOS,
- integrated circuit,
- inverter,
- NAND,
- metal interconnect
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References
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