Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Zhenzhen Kong; Hongxiao Lin; Hailing Wang; Yanpeng Song; Junjie Li; Xiaomeng Liu; Anyan Du; Yuanhao Miao; Yiwen Zhang; Yuhui Ren; Chen Li; Jiahan Yu; Jinbiao Liu; Jingxiong Liu; Qinzhu Zhang; Jianfeng Gao; Huihui Li; Xiangsheng Wang; Junfeng Li; Henry H. Radamson; Chao Zhao; Tianchun Ye; Guilei Wang

doi:10.1088/1674-4926/44/12/124101

J. Semicond. > 2023, Volume 44 > Issue 12 > 124101, doi: 10.1088/1674-4926/44/12/124101

ARTICLES

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Zhenzhen Kong^{1, 4}, Hongxiao Lin^{3, 4}, Hailing Wang², Yanpeng Song², Junjie Li¹, Xiaomeng Liu², Anyan Du¹, Yuanhao Miao^{1, 3}, Yiwen Zhang^{1, 4}, Yuhui Ren^{1, 4}, Chen Li^{1, 4}, Jiahan Yu^{1, 4}, Jinbiao Liu^{1, 4}, Jingxiong Liu^{1, 4}, Qinzhu Zhang¹, Jianfeng Gao¹, Huihui Li², Xiangsheng Wang², Junfeng Li¹, Henry H. Radamson³, Chao Zhao², Tianchun Ye^{1, 4} and Guilei Wang^{2, 5,}

+ Author Affiliations

Corresponding author: Guilei Wang, Guilei.Wang@bjsamt.org.cn

Abstract: Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

Key words: RPCVD, epitaxy, SiGe/Si multilayers, L-GAAFETs, VS-DRAM

References

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Fig. 1. (Color online) (a) Si/SiGe epitaxy; (b) SiGe full release; (c) high-k and top electrode deposition.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) (a) Process flow. Schematic diagram of (b) hard mask growth, (c) anisotropic vertical etching of SiGe/Si MLs, and (d) isotropic selective lateral etching of SiGe.

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Fig. 3. (Color online) TEM images of ML structures with SiGe layers of (a) 20 nm, (b) 40 nm and (c) 60 nm. SIMS profile of (d) Ge concentration and (e) the thickness of SiGe layers in three 15-period Si/SiGe ML structures.

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Fig. 4. (a) Rocking curves (RCs) of ML structures with different SiGe layer thicknesses. RSM images of ML structures with (b) 20 nm SiGe layers, (c) 40 nm SiGe layers and (d) 60 nm SiGe layers. β₁ ≈ 6.7°, β₂ ≈ 10°.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) TEM images of ML structures with (a) 20 nm SiGe layers, (b) 40 nm SiGe layers and (c) 60 nm SiGe layers. HRTEM cross-sectional images of ML structures with (d) 20 nm SiGe layers, (e) 40 nm SiGe layers and (f) 60 nm SiGe layers.

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Fig. 6. SEM cross-sectional images of (a) 25 s dry etch, (b) 25 s continuous wet etch and (c) 40 cycles of ALE for the ML structure with 40 nm SiGe layers.

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Fig. 7. (Color online) (a) Rocking curves of SiGe (20 nm)/Si ML structures at different steps of processing. RSMs in the vicinity of the asymmetric (113) Bragg reflection acquired on SiGe (20 nm)/Si ML structures: (b) as-grown, (c) after vertical anisotropy etching and (d) after lateral isotropic SiGe selectivity dry etching α₁ ≈ 3°, α₂ ≈ 4°.

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Table 1. Selective etches of SiGe to Si.

Method	Solution	Advantages	Problem
Thermal etching	HCl^[38−40] ClF₃^[41]	High selectivity	React in chemical vapor deposition (CVD) tool The etching accuracy is limited Different etch rates for different crystal orientations
Dry etching	CF₄/N₂/O₂^[27] CF₄/O₂/He^[20] NF₃/O₂/N₂^[42]	Easy to use in large wafer size Isotropic Fast	The etching accuracy is limited
Continuous wet etching	HF/HNO₃/CH₃COOH^[25] HF/HNO₃/CH₃COOH/H₂O^[31]	Excellent selectivity High etch rate Uniform etch rate in MLs etching	Etch rate depends strongly on the Ge content Residues block the tunnel in MLs etching
Continuous wet etching	HF/H₂O₂/CH₃COOH^[43−45] HF/H₂O₂/CH₃COOH/H₂O^[46]	High etch rate Nanoscale etching of SiGe to Si	Not suitable for small size Long aging time
Wet ALE	H₂O₂/BOEs^[47] HNO₃/BOEs^[48]	Controllable etch rate Atomically smooth surfaces	Long circle time Multistep processes Surface tension and capillary effect

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[1]	Radamson H H, Zhu H L, Wu Z H, et al. State of the art and future perspectives in advanced CMOS technology. Nanomaterials (Basel), 2020, 10, 1555 doi: 10.3390/nano10081555
[2]	Radamson H H, Simeon E. CMOS past, present and future. Amsterdam: Elsevier, 2018, 105
[3]	Loubet N, Kal S, Alix C, et al. A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around NanoSheet devices. 2019 IEEE International Electron Devices Meeting (IEDM), 2020, 11.4. 1 doi: 10.1109/IEDM19573.2019.8993615
[4]	Radamson H H, Zhang Y B, He X B, et al. The challenges of advanced CMOS process from 2D to 3D. Appl Sci, 2017, 7, 1047 doi: 10.3390/app7101047
[5]	Radamson H H, He X B, Zhang Q Z, et al. Miniaturization of cmos. Micromachines, 2019, 10, 293 doi: 10.3390/mi10050293
[6]	Radamson H H, Joelsson K B, Ni W X, et al. Characterization of highly boron-doped Si, Si_{1− x}Ge_x and Ge layers by high-resolution transmission electron microscopy. J Cryst Growth, 1995, 157, 80 doi: 10.1016/0022-0248(95)00375-4
[7]	Wang G L, Luo J, Qin C L, et al. Integration of highly strained SiGe in source and drain with HK and MG for 22 nm bulk PMOS transistors. Nanoscale Res Lett, 2017, 12, 123 doi: 10.1186/s11671-017-1908-0
[8]	Singh N, Buddharaju K D, Manhas S K, et al. Si, SiGe nanowire devices by top–down technology and their applications. IEEE Trans Electron Devices, 2008, 55, 3107 doi: 10.1109/TED.2008.2005154
[9]	Barraud S, Previtali B, Lapras V, et al. Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies. Semicond Sci Technol, 2019, 34, 074001 doi: 10.1088/1361-6641/ab1e5b
[10]	Radamson H H, Kolahdouz M. Selective epitaxy growth of Si_{1− x}Ge_x layers for MOSFETs and FinFETs. J Mater Sci: Mater Electron, 2015, 26, 4584 doi: 10.1007/s10854-015-3123-z
[11]	Chu C L, Wu K, Luo G L, et al. Stacked Ge-nanosheet GAAFETs fabricated by Ge/Si multilayer epitaxy. IEEE Electron Device Lett, 2018, 39, 1133 doi: 10.1109/LED.2018.2850366
[12]	Veloso A, Paraschiv V, Vecchio E, et al. (invited) challenges on surface conditioning in 3D device architectures: Triple-gate FinFETs, gate-all-around lateral and vertical nanowire FETs. ECS Trans, 2017, 80, 3 doi: 10.1149/08002.0003ecst
[13]	Neisser M. International roadmap for devices and systems lithography roadmap. J Micro/nanopatterning Mater Metrol, 2021, 20, 44601 doi: 10.1117/1.JMM.20.4.044601
[14]	Ha D, Kim H S. Prospective innovation of DRAM, flash, and logic technologies for digital transformation (DX) era. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, 417 doi: 10.1109/VLSITechnologyandCir46769.2022.9830465
[15]	Huang M, Si S F, He Z, et al. A 3D stackable 1T1C DRAM: Architecture, process integration and circuit simulation. 2023 IEEE International Memory Workshop (IMW), 2023, 1 doi: 10.1109/IMW56887.2023.10145931
[16]	Han J W, Park S H, Jeong M Y, et al. Ongoing evolution of DRAM scaling via third dimension-vertically stacked DRAM . 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, 1 doi: 10.23919/VLSITechnologyandCir57934.2023.10185290
[17]	Rachidi S, Campo A, Loup V, et al. Isotropic dry etching of Si selectively to Si_0.7Ge_0.3 for CMOS sub-10 nm applications. J Vac Sci Technol A Vac Surf Films, 2020, 38, 033002 doi: 10.1116/1.5143118
[18]	Huynh-Bao T, Sakhare S, Yakimets D, et al. A comprehensive benchmark and optimization of 5-nm lateral and vertical GAA 6T-SRAMs. IEEE Trans Electron Devices, 2016, 63, 643 doi: 10.1109/TED.2015.2504729
[19]	Liu Y C, Tu C T, Tsai C E, et al. First highly stacked Ge_0.95Si_0.05 nGAAFETs with record ION = 110 μA (4100 μA/μm) at VOV=VDS=0.5V and high Gm, max = 340 μS (13000 μS/μm) at VDS=0.5V by wet etching. 2021 Symposium on VLSI Technology, 2021, 1
[20]	Li J J, Wang W W, Li Y L, et al. Study of selective isotropic etching Si_{1− x}Ge_x in process of nanowire transistors. J Mater Sci:Mater Electron, 2020, 31, 134 doi: 10.1007/s10854-019-02269-x
[21]	Lee S, Jeong J, Yoon J S, et al. Sensitivity of inner spacer thickness variations for sub-3-nm node silicon nanosheet field-effect transistors. Nanomaterials, 2022, 12, 3349 doi: 10.3390/nano12193349
[22]	Reboh S, Coquand R, Barraud S, et al. Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology. Appl Phys Lett, 2018, 112, 051901 doi: 10.1063/1.5010997
[23]	Tuppen C G, Gibbings C J, Hockly M. Mismatch dislocation nucleation and propagation in Si/Si_{1− x}Ge_x heterostructures. MRS Proc, 1988, 130, 185 doi: 10.1557/PROC-130-185
[24]	Barbisan L, Marzegalli A, Montalenti F. Atomic-scale insights on the formation of ordered arrays of edge dislocations in Ge/Si(001) films via molecular dynamics simulations. Sci Rep, 2022, 12, 3235 doi: 10.1038/s41598-022-07206-3
[25]	Orlowski M, Ndoye C, Liu T, et al. (invited) Si, SiGe, Ge, and III-V semiconductor nanomembranes and nanowires enabled by SiGe epitaxy. ECS Trans, 2010, 33, 777 doi: 10.1149/1.3487608
[26]	Borel S, Arvet C, Bilde J, et al. Isotropic etching of SiGe alloys with high selectivity to similar materials. Microelectron Eng, 2004, 73/74, 301 doi: 10.1016/S0167-9317(04)00115-7
[27]	Caubet V, Beylier C, Borel S, et al. Mechanisms of isotropic and selective etching between SiGe and Si. J Vac Sci Technol B Microelectron Nanometer Struct Process Meas Phenom, 2006, 24, 2748 doi: 10.1116/1.2393244
[28]	Zhao Y, Iwase T, Satake M, et al. Formation mechanism of rounded SiGe-etch front in isotropic SiGe plasma etching for gate-all-around FETs. IEEE J Electron Devices Soc, 2021, 9, 1112 doi: 10.1109/JEDS.2021.3130916
[29]	Chang W Y, Luo G L, Huang Y S, et al. SiGe and Si gate-all-around FET fabricated by selective etching the same epitaxial layers. 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2022, 21 doi: 10.1109/EDTM53872.2022.9797991
[30]	Wostyn K, Sebaai F, Rip J, et al. (invited) selective etch of Si and SiGe for gate all-around device architecture. ECS Trans, 2015, 69, 147 doi: 10.1149/06908.0147ecst
[31]	Choi Y, Jang H, Byun D S, et al. Selective chemical wet etching of Si_{1- x}Ge_x versus Si in single-layer and multi-layer with HNO₃/HF mixtures. Thin Solid Films, 2020, 709, 138230 doi: 10.1016/j.tsf.2020.138230
[32]	Kim S, Kim M, Ryu D, et al. Investigation of electrical characteristic behavior induced by channel-release process in stacked nanosheet gate-all-around MOSFETs. IEEE Trans Electron Devices, 2020, 67, 2648 doi: 10.1109/TED.2020.2989416
[33]	Zhuge J, Wang R S, Huang R, et al. Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology. 2009 IEEE International Electron Devices Meeting (IEDM), 2010, 1 doi: 10.1109/IEDM.2009.5424421
[34]	Sous S A, Hildmann B O, Kaysser W A. Characterization of dislocation densities in germanium and silicon single crystals by high resolution X-ray diffraction. Phys Stat Sol (a), 1997, 159, 343 doi: 10.1002/1521-396X(199702)159:2<343::AID-PSSA343>3.0.CO;2-#
[35]	Radamson H H, Moeen M, Abedin A, et al. Sensitivity of signal-to-noise ratio to the layer profile and crystal quality of SiGe/Si multilayers. ECS J Solid State Sci Technol, 2016, 5, P3196 doi: 10.1149/2.0261604jss
[36]	Hartmann J M, Papon A M, Barnes J P, et al. Growth kinetics of SiGe/Si superlattices on bulk and silicon-on-insulator substrates for multi-channel devices. J Cryst Growth, 2009, 311, 3152 doi: 10.1016/j.jcrysgro.2009.03.027
[37]	Radamson H H, Hållstedt J. Application of high-resolution X-ray diffraction for detecting defects in SiGe(C) materials. J Phys: Condens Matter, 2005, 17, S2315 doi: 10.1088/0953-8984/17/22/020
[38]	Destefanis V, Hartmann J M, Hopstaken M, et al. Low-thermal surface preparation, HCl etch and Si/SiGe selective epitaxy on (1 1 0) silicon surfaces. Semicond Sci Technol, 2008, 23, 105018 doi: 10.1088/0268-1242/23/10/105018
[39]	Loubet N, Kormann T, Chabanne G, et al. Selective etching of Si_{1− x}Ge_x versus Si with gaseous HCl for the formation of advanced CMOS devices. Thin Solid Films, 2008, 517, 93 doi: 10.1016/j.tsf.2008.08.081
[40]	Mertens H, Ritzenthaler R, Hikavyy A, et al. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates. 2016 IEEE Symposium on VLSI Technology, 2016, 1 doi: 10.1109/VLSIT.2016.7573416
[41]	Tsai Y H, Wang M M. Fundamental study on the selective etching of SiGe and Si in ClF₃ gas for nanosheet gate-all-around transistor manufacturing: A first principle study. J Vac Sci Technol B, 2022, 40, 013201 doi: 10.1116/6.0001455
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Received: 07 July 2023 Revised: 05 August 2023 Online: Accepted Manuscript: 13 September 2023Uncorrected proof: 21 November 2023Published: 10 December 2023

Article Navigation > Journal of Semiconductors > 2023 > 44(12): 124101

Zhenzhen Kong, Hongxiao Lin, Hailing Wang, Yanpeng Song, Junjie Li, Xiaomeng Liu, Anyan Du, Yuanhao Miao, Yiwen Zhang, Yuhui Ren, Chen Li, Jiahan Yu, Jinbiao Liu, Jingxiong Liu, Qinzhu Zhang, Jianfeng Gao, Huihui Li, Xiangsheng Wang, Junfeng Li, Henry H. Radamson, Chao Zhao, Tianchun Ye, Guilei Wang. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM[J]. Journal of Semiconductors, 2023, 44(12): 124101. doi: 10.1088/1674-4926/44/12/124101 Z Z Kong, H X Lin, H L Wang, Y P Song, J J Li, X M Liu, A Y Du, Y H Miao, Y W Zhang, Y H Ren, C Li, J H Yu, J B Liu, J X Liu, Q Z Zhang, J F Gao, H H Li, X S Wang, J F Li, H H Radamson, C Zhao, T C Ye, G L Wang. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM[J]. J. Semicond, 2023, 44(12): 124101. doi: 10.1088/1674-4926/44/12/124101Export: BibTex EndNote

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Z Z Kong, H X Lin, H L Wang, Y P Song, J J Li, X M Liu, A Y Du, Y H Miao, Y W Zhang, Y H Ren, C Li, J H Yu, J B Liu, J X Liu, Q Z Zhang, J F Gao, H H Li, X S Wang, J F Li, H H Radamson, C Zhao, T C Ye, G L Wang. Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM[J]. J. Semicond, 2023, 44(12): 124101. doi: 10.1088/1674-4926/44/12/124101

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Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

doi: 10.1088/1674-4926/44/12/124101

1.
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
2.
Beijing Superstring Academy of Memory Technology, Beijing 100176, China
3.
Research and Development Center of Optoelectronic Hybrid IC, Guangdong Greater Bay Area Institute of Integrated Circuit and System, Guangzhou 510535, China
4.
Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China
5.
Hefei National Laboratory, Hefei 230088, China

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Author Bio:
Zhenzhen Kong Zhenzhen Kong received her BS in 2012. She is now a PhD student at University of Chinese Academy of Sciences under the supervision of Prof. Tianchun Ye, Prof. Henry H. Radamson and Prof. Guilei Wang. Her research focuses on growth of Group Ⅳ for high mobility ultra-thin body MOSFET and quantum computing devices

Guilei Wang Guilei Wang received his Bachelor's degree in 2005 and his PhD in 2016 from the University of Chinese Academy of Sciences. He has been worked as a professor at the Integrated Circuit Advanced Process Center at the Chinese Academy of Sciences until 2021. In October 2021, he joined the Beijing Superstring Academy of Memory Technology as a full professor. His research interests are focused on new materials, devices, and process integration for the IC industry
Corresponding author: Guilei.Wang@bjsamt.org.cn
Received Date: 2023-07-07
Revised Date: 2023-08-05

Available Online: 2023-09-13

Abstract

Abstract

Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.
- RPCVD,
- epitaxy,
- SiGe/Si multilayers,
- L-GAAFETs,
- VS-DRAM

Supplementary materials to this article can be found online at https://doi.org/10.1088/1674-4926/44/12/124101.

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References(48)

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