J. Semicond. > 2023, Volume 44 > Issue 5 > 054101, doi: 10.1088/1674-4926/44/5/054101

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Flash-based in-memory computing for stochastic computing in image edge detection

Zhaohui Sun1, Yang Feng1, Peng Guo2, Zheng Dong1, Junyu Zhang3, Jing Liu4, Xuepeng Zhan1, Jixuan Wu1 and Jiezhi Chen1,

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 Corresponding author: Jiezhi Chen, chen.jiezhi@sdu.edu.cn

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Abstract: The “memory wall” of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution, while in-memory computing (IMC) architecture is a promising approach to breaking the bottleneck. Although variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures, stochastic computing (SC) can compensate for these shortcomings due to its low sensitivity to cell disturbances. Furthermore, massive parallel computing can be processed to improve the speed and efficiency of the system. In this paper, by designing logic functions in NOR flash arrays, SC in IMC for the image edge detection is realized, demonstrating ultra-low computational complexity and power consumption (25.5 fJ/pixel at 2-bit sequence length). More impressively, the noise immunity is 6 times higher than that of the traditional binary method, showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.

Key words: in-memory computing, stochastic computing, NOR flash memory, image edge detection



[1]
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[3]
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[4]
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[5]
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[6]
Xiong H, He G. Hardware implementation of an improved stochastic computing based deep neural network using short sequence length. IEEE Trans Circuits Syst II, 2020, 67(11), 2667 doi: 10.1109/TCSII.2020.2969691
[7]
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[8]
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[9]
Gonzalez, Rafael C, Digital image processing. Pearson education India. 3rd ed. , 2009, 242
[10]
Feng Y, Chen B, Liu J, et al. Design-technology co-optimizations (DTCO) for general-purpose computing in-memory based on 55nm NOR flash technology. 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 12.1.1 doi: 10.1109/IEDM19574.2021.9720625
[11]
Kingra S K, Parmar V, Chang C C, et al. SLIM: simultaneous logic-in-memory computing exploiting bilayer analog OxRAM devices. Sci Rep, 2020, 10(1), 1 doi: 10.1038/s41598-019-56847-4
[12]
Lee J, Park B G, Kim Y. Implementation of boolean logic functions in charge trap flash for in-memory computing. IEEE Electron Device Lett, 2019, 40(9), 1358 doi: 10.1109/LED.2019.2928335
[13]
Milo V, Malavena G, Monzio Compagnoni C, et al. Memristive and CMOS devices for neuromorphic computing. Materials, 2020, 13(1), 166 doi: 10.3390/ma13010166
[14]
Yao P, Wu H, Gao B, et al. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577(7792), 641 doi: 10.1038/s41586-020-1942-4
Fig. 1.  (Color online) (a) Comparison between conventional and SC methods, SNs length = N bits. (b) Region of the image. (c) The stochastic computational element to realize image detection algorithmic in logic circuits. (d) Scaled addition realized by the OR gate, scaled subtraction, and absolute value calculation realized by the XOR gate. (e) The data processing flow chart in the proposed method.

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Fig. 2.  (Color online) (a) The NOR flash architecture for logic operation. (b) I–V curve for NOR flash array. (c) Memory window degradation by P/E cycling. (d) Read current fluctuations can be observed caused by RTN.

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Fig. 3.  (Color online) (a) BER comparison between the conventional method and SC method when the signal noise is considered. (b) Effects of simultaneous offset of device parameters VG/VD/Vth on BER. (c) RTN effects are ignorable on BER. (d) Add 10% noise in (b). (e) Under different VG/VD conditions, effects of simultaneous 10% drift of three device parameters on BER(N = 2). (f) Effects of Vth shifts.

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Fig. 4.  (Color online) (a) BER and (b) power consumption at various VG/VD voltages when N = 2.

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Table 1.   XOR truth table (VD = 1 V).

xi1xi2VG (V)Vth (V)Device stateLogical value
0034CLOSE0
0132Sub-saturation1
1102CLOSE0
DownLoad: CSV

Table 2.   OR truth table (VG = 3 V, VD = 1 V).

xi2Vth (V)Device stateLogical value
04CLOSE0
12Sub-saturation1
DownLoad: CSV
[1]
Wang Y, Yang Y, Hao Y, et al. Embracing the era of neuromorphic computing. J Semicond, 2021, 42(1), 010301 doi: 10.1088/1674-4926/42/1/010301
[2]
Hao Y, Wu H, Yang Y, et al. Preface to the special issue on beyond moore: Resistive switching devices for emerging memory and neuromorphic computing. J Semicond, 2021, 42(1), 010101 doi: 10.1088/1674-4926/42/1/010101
[3]
Lue H T, Hsu P K, Wei M L, et al. Optimal design methods to transform 3D NAND flash into a high-density, high-bandwidth and low-power nonvolatile computing in memory (nvCIM) accelerator for deep-learning neural networks (DNN). 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 38.1.1 doi: 10.1109/IEDM19573.2019.8993652
[4]
Li P, Lilja D J. Using stochastic computing to implement digital image processing algorithms. 2011 IEEE 29th International Conference on Computer Design (ICCD), 2011, 154 doi: 10.1109/ICCD.2011.6081391
[5]
Zhang Y, Wang R, Jiang X, et al. Design guidelines of stochastic computing based on FinFET: A technology-circuit perspective. 2017 IEEE International Electron Devices Meeting (IEDM), 2017, 6.6.1 doi: 10.1109/IEDM.2017.8268342
[6]
Xiong H, He G. Hardware implementation of an improved stochastic computing based deep neural network using short sequence length. IEEE Trans Circuits Syst II, 2020, 67(11), 2667 doi: 10.1109/TCSII.2020.2969691
[7]
Otsu N. A threshold selection method from gray-level histograms. IEEE Trans Syst, Man, Cyber, 1979, 9(1), 62 doi: 10.1109/TSMC.1979.4310076
[8]
Mendiratta N, Tripathi S L. A review on performance comparison of advanced MOSFET structures below 45 nm technology node. J Semicond, 2020, 41(6), 061401 doi: 10.1088/1674-4926/41/6/061401
[9]
Gonzalez, Rafael C, Digital image processing. Pearson education India. 3rd ed. , 2009, 242
[10]
Feng Y, Chen B, Liu J, et al. Design-technology co-optimizations (DTCO) for general-purpose computing in-memory based on 55nm NOR flash technology. 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 12.1.1 doi: 10.1109/IEDM19574.2021.9720625
[11]
Kingra S K, Parmar V, Chang C C, et al. SLIM: simultaneous logic-in-memory computing exploiting bilayer analog OxRAM devices. Sci Rep, 2020, 10(1), 1 doi: 10.1038/s41598-019-56847-4
[12]
Lee J, Park B G, Kim Y. Implementation of boolean logic functions in charge trap flash for in-memory computing. IEEE Electron Device Lett, 2019, 40(9), 1358 doi: 10.1109/LED.2019.2928335
[13]
Milo V, Malavena G, Monzio Compagnoni C, et al. Memristive and CMOS devices for neuromorphic computing. Materials, 2020, 13(1), 166 doi: 10.3390/ma13010166
[14]
Yao P, Wu H, Gao B, et al. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577(7792), 641 doi: 10.1038/s41586-020-1942-4

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    Received: 05 December 2022 Revised: 28 December 2022 Online: Accepted Manuscript: 22 February 2023Uncorrected proof: 23 February 2023Published: 10 May 2023

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      Article Navigation >  Journal of Semiconductors  > 2023  >  44(5): 054101
      Zhaohui Sun, Yang Feng, Peng Guo, Zheng Dong, Junyu Zhang, Jing Liu, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen. Flash-based in-memory computing for stochastic computing in image edge detection[J]. Journal of Semiconductors, 2023, 44(5): 054101. doi: 10.1088/1674-4926/44/5/054101 Z H Sun, Y Feng, P Guo, Z Dong, J Y Zhang, J Liu, X P Zhan, J X Wu, J Z Chen. Flash-based in-memory computing for stochastic computing in image edge detection[J]. J. Semicond, 2023, 44(5): 054101. doi: 10.1088/1674-4926/44/5/054101Export: BibTex EndNote
      Citation:
      Zhaohui Sun, Yang Feng, Peng Guo, Zheng Dong, Junyu Zhang, Jing Liu, Xuepeng Zhan, Jixuan Wu, Jiezhi Chen. Flash-based in-memory computing for stochastic computing in image edge detection[J]. Journal of Semiconductors, 2023, 44(5): 054101. doi: 10.1088/1674-4926/44/5/054101

      Z H Sun, Y Feng, P Guo, Z Dong, J Y Zhang, J Liu, X P Zhan, J X Wu, J Z Chen. Flash-based in-memory computing for stochastic computing in image edge detection[J]. J. Semicond, 2023, 44(5): 054101. doi: 10.1088/1674-4926/44/5/054101
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      Flash-based in-memory computing for stochastic computing in image edge detection

      doi: 10.1088/1674-4926/44/5/054101
      • 1.

        School of Information Science and Engineering (ISE), Shandong University, Qingdao 266000, China

      • 2.

        Shandong Sinochip Semiconductors Co. Ltd, Jinan 250101, China

      • 3.

        Neumem Co., Ltd, Hefei 230088, China

      • 4.

        Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China

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      • Author Bio:

        Zhaohui Sun got her B.S. from Shandong University in 2018. Now she is an M.S. student at Shandong University under the supervision of Prof. Jiezhi Chen. Her research focuses on in-memory computing and NOR Flash device reliability

        Jiezhi Chen received the Ph.D. degree from the Department of Informatics and Electronics, the University of Tokyo, in 2009. He is currently a Professor at the School of Information Science and Engineering, Shandong University, China. His research interests include flash memory, emerging non-volatile memories, nanoscale transistors, and computing-in-memory architectures, with the main focus on reliability physics and optimization strategies

      • Corresponding author: chen.jiezhi@sdu.edu.cn
      • Received Date: 2022-12-05
      • Revised Date: 2022-12-28
        • Available Online: 2023-02-22

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