In this paper, we explore the electrical characteristics of high-electron-mobility transistors (HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor (MIS) structure. The high-resistance tantalum nitride (TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10⁻⁷ mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Memristors as non-volatile memory devices have gained numerous attentions owing to their advantages in storage, in-memory computing, synaptic applications, etc. In recent years, two-dimensional (2D) materials with moderate defects have been discovered to exist memristive feature. However, it is very difficult to obtain moderate defect degree in 2D materials, and studied on modulation means and mechanism becomes urgent and essential. In this work, we realized memristive feature with a bipolar switching and a configurable on/off ratio in a two-terminal MoS₂ device (on/off ratio ~100), for the first time, from absent to present using laser-modulation to few-layer defect-free MoS₂ (about 10 layers), and its retention time in both high resistance state and low resistance state can reach 2 × 10⁴ s. The mechanism of the laser-induced memristive feature has been cleared by dynamic Monte Carlo simulations and first-principles calculations. Furthermore, we verified the universality of the laser-modulation by investigating other 2D materials of TMDs. Our work will open a route to modulate and optimize the performance of 2D semiconductor memristive devices.

A frequency servo system-on-chip (FS-SoC) featuring output power stabilization technology is introduced in this study for high-precision and miniaturized cesium (Cs) atomic clocks. The proposed power stabilization loop (PSL) technique, incorporating an off-chip power detector (PD), ensures that the output power of the FS-SoC remains stable, mitigating the impact of power fluctuations on the atomic clock's stability. Additionally, a one-pulse-per-second (1PPS) is employed to synchronize the clock with GPS. Fabricated using 65 nm CMOS technology, the measured phase noise of the FS-SoC stands at −69.5 dBc/Hz@100 Hz offset and −83.9 dBc/Hz@1 kHz offset, accompanied by a power dissipation of 19.7 mW. The Cs atomic clock employing the proposed FS-SoC and PSL obtains an Allan deviation of 1.7 × 10⁻¹¹ with 1-s averaging time.

Robots are widely used, providing significant convenience in daily life and production. With the rapid development of artificial intelligence and neuromorphic computing in recent years, the realization of more intelligent robots through a profound intersection of neuroscience and robotics has received much attention. Neuromorphic circuits based on memristors used to construct hardware neural networks have proved to be a promising solution of shattering traditional control limitations in the field of robot control, showcasing characteristics that enhance robot intelligence, speed, and energy efficiency. Starting with introducing the working mechanism of memristors and peripheral circuit design, this review gives a comprehensive analysis on the biomimetic information processing and biomimetic driving operations achieved through the utilization of neuromorphic circuits in brain-like control. Four hardware neural network approaches, including digital-analog hybrid circuit design, novel device structure design, multi-regulation mechanism, and crossbar array, are summarized, which can well simulate the motor decision-making mechanism, multi-information integration and parallel control of brain at the hardware level. It will be definitely conductive to promote the application of memristor-based neuromorphic circuits in areas such as intelligent robotics, artificial intelligence, and neural computing. Finally, a conclusion and future prospects are discussed.

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

In this paper, an NMOS output-capacitorless low-dropout regulator (OCL-LDO) featuring dual-loop regulation has been proposed, achieving fast transient response with low power consumption. An event-driven charge pump (CP) loop with the dynamic strength control (DSC), is proposed in this paper, which overcomes trade-offs inherent in conventional structures. The presented design addresses and resolves the large signal stability issue, which has been previously overlooked in the event-driven charge pump structure. This breakthrough allows for the full exploitation of the charge-pump structure's potential, particularly in enhancing transient recovery. Moreover, a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage, leading to favorable static characteristics. A prototype chip has been fabricated in 65 nm CMOS technology. The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current (I_Q) and can recover within 30 ns under 200 mA/10 ns loading change.

Growth of gallium nitride (GaN) inverted pyramids on c-plane sapphire substrates is benefit for fabricating novel devices as it forms the semipolar facets. In this work, GaN inverted pyramids are directly grown on c-plane patterned sapphire substrates (PSS) by metal organic vapor phase epitaxy (MOVPE). The influences of growth conditions on the surface morphology are experimentally studied and explained by Wulff constructions. The competition of growth rate among {0001}, {$ 10\bar{\text{1}}1 $}, and {$11 \bar{\text{2}}2 $} facets results in the various surface morphologies of GaN. A higher growth temperature of 985 °C and a lower Ⅴ/Ⅲ ratio of 25 can expand the area of {$ 11\bar{\text{2}}2 $} facets in GaN inverted pyramids. On the other hand, GaN inverted pyramids with almost pure {$10 \bar{\text{1}}1 $} facets are obtained by using a lower growth temperature of 930 °C, a higher Ⅴ/Ⅲ ratio of 100, and PSS with pattern arrangement perpendicular to the substrate primary flat.

Two-dimensional (2D) materials have attracted tremendous interest in view of the outstanding optoelectronic properties, showing new possibilities for future photovoltaic devices toward high performance, high specific power and flexibility. In recent years, substantial works have focused on 2D photovoltaic devices, and great progress has been achieved. Here, we present the review of recent advances in 2D photovoltaic devices, focusing on 2D-material-based Schottky junctions, homojunctions, 2D−2D heterojunctions, 2D−3D heterojunctions, and bulk photovoltaic effect devices. Furthermore, advanced strategies for improving the photovoltaic performances are demonstrated in detail. Finally, conclusions and outlooks are delivered, providing a guideline for the further development of 2D photovoltaic devices.

An accurate and novel small-signal equivalent circuit model for GaN high-electron-mobility transistors (HEMTs) is proposed, which considers a dual-field-plate (FP) made up of a gate-FP and a source-FP. The equivalent circuit of the overall model is composed of parasitic elements, intrinsic transistors, gate-FP, and source-FP networks. The equivalent circuit of the gate-FP is identical to that of the intrinsic transistor. In order to simplify the complexity of the model, a series combination of a resistor and a capacitor is employed to represent the source-FP. The analytical extraction procedure of the model parameters is presented based on the proposed equivalent circuit. The verification is carried out on a 4 × 250 μm GaN HEMT device with a gate-FP and a source-FP in a 0.45 μm technology. Compared with the classic model, the proposed novel small-signal model shows closer agreement with measured S-parameters in the range of 1.0 to 18.0 GHz.

This work reports the growth and characterization of p-AlInN layers doped with Mg by plasma-assisted molecular beam epitaxy (PAMBE). AlInN was grown with an Al molar fraction of 0.80 by metal-modulated epitaxy (MME) with a thickness of 180 nm on Si(111) substrates using AlN as buffer layers. Low substrate temperatures were used to enhance the incorporation of indium atoms into the alloy without clustering, as confirmed by X-ray diffraction (XRD). Cathodoluminescence measurements revealed ultraviolet (UV) range emissions. Meanwhile, Hall effect measurements indicated a maximum hole mobility of 146 cm²/(V∙s), corresponding to a free hole concentration of 1.23 × 10¹⁹ cm⁻³. The samples were analyzed by X-ray photoelectron spectroscopy (XPS) estimating the alloy composition and extracting the Fermi level by valence band analysis. Mg-doped AlInN layers were studied for use as the electron-blocking layer (EBL) in LED structures. We varied the Al composition in the EBL from 0.84 to 0.96 molar fraction to assess its theoretical effects on electroluminescence, carrier concentration, and electric field, using SILVACO Atlas. The results from this study highlight the importance and capability of producing high-quality Mg-doped p-AlInN layers through PAMBE. Our simulations suggest that an Al content of 0.86 is optimal for achieving desired outcomes in electroluminescence, carrier concentration, and electric field.

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

High quality β-Ga₂O₃ single crystal nanobelts with length of 2−3 mm and width from tens of microns to 132 μm were synthesized by carbothermal reduction method. Based on the grown nanobelt with the length of 600 μm, the dual-Schottky-junctions coupling device (DSCD) was fabricated. Due to the electrically floating Ga₂O₃ nanobelt region coupling with the double Schottky-junctions, the current I_S2 increases firstly and rapidly reaches into saturation as increase the voltage V_S2. The saturation current is about 10 pA, which is two orders of magnitude lower than that of a single Schottky-junction. In the case of solar-blind ultraviolet (UV) light irradiation, the photogenerated electrons further aggravate the coupling physical mechanism in device. I_S2 increases as the intensity of UV light increases. Under the UV light of 1820 μW/cm², I_S2 quickly enters the saturation state. At V_S2 = 10 V, photo-to-dark current ratio (PDCR) of the device reaches more than 10⁴, the external quantum efficiency (EQE) is 1.6 × 10³%, and the detectivity (D^*) is 7.5 × 10¹² Jones. In addition, the device has a very short rise and decay times of 25−54 ms under different positive and negative bias. DSCD shows unique electrical and optical control characteristics, which will open a new way for the application of nanobelt-based devices.

Two-dimension (2D) van der Waals heterojunction holds essential promise in achieving high-performance flexible near-infrared (NIR) photodetector. Here, we report the successful fabrication of ZnSb/Ti₃C₂T_x MXene based flexible NIR photodetector array via a facile photolithography technology. The single ZnSb/Ti₃C₂T_x photodetector exhibited a high light-to-dark current ratio of 4.98, fast response/recovery time (2.5/1.3 s) and excellent stability due to the tight connection between 2D ZnSb nanoplates and 2D Ti₃C₂T_x MXene nanoflakes, and the formed 2D van der Waals heterojunction. Thin polyethylene terephthalate (PET) substrate enables the ZnSb/Ti₃C₂T_x photodetector withstand bending such that stable photoelectrical properties with non-obvious change were maintained over 5000 bending cycles. Moreover, the ZnSb/Ti₃C₂T_x photodetectors were integrated into a 26 × 5 device array, realizing a NIR image sensing application.

Radiation damage produced in 4H-SiC by electrons of different doses is presented by using multiple characterization techniques. Raman spectra results indicate that SiC crystal structures are essentially impervious to 10 MeV electron irradiation with doses up to 3000 kGy. However, irradiation indead leads to the generation of various defects, which are evaluated through photoluminescence (PL) and deep level transient spectroscopy (DLTS). The PL spectra feature a prominent broad band centered at 500 nm, accompanied by several smaller peaks ranging from 660 to 808 nm. The intensity of each PL peak demonstrates a linear correlation with the irradiation dose, indicating a proportional increase in defect concentration during irradiation. DLTS spectra reveal several thermally unstable and stable defects that exhibit similarities at low irradiation doses. Notably, after irradiating at the higher dose of 1000 kGy, a new stable defect labeled as R₂ (Ec − 0.51 eV) appeared after annealing at 800 K. Furthermore, the impact of irradiation-induced defects on SiC junction barrier Schottky diodes is discussed. It is observed that high-dose electron irradiation converts SiC n-epilayers to semi-insulating layers. However, subjecting the samples to a temperature of only 800 K results in a significant reduction in resistance due to the annealing out of unstable defects.

All-dielectric metasurface, which features low optical absorptance and high resolution, is becoming a promising candidate for full-color generation. However, the optical response of current metamaterials is fixed and lacks active tuning. In this work, we demonstrate a reconfigurable and polarization-dependent active color generation technique by incorporating low-loss phase change materials (PCMs) and CaF₂ all-dielectric substrate. Based on the strong Mie resonance effect and low optical absorption structure, a transflective, full-color with high color purity and gamut value is achieved. The spectrum can be dynamically manipulated by changing either the polarization of incident light or the PCM state. High transmittance and reflectance can be simultaneously achieved by using low-loss PCMs and substrate. The novel active metasurfaces can bring new inspiration in the areas of optical encryption, anti-counterfeiting, and display technologies.

Avalanche photodetectors (APDs) featuring an avalanche multiplication region are vital for reaching high sensitivity and responsivity in optical transceivers. Waveguide-coupled Ge-on-Si separate absorption, charge, and multiplication (SACM) APDs are popular due to their straightforward fabrication process, low optical propagation loss, and high detection sensitivity in optical communications. This paper introduces a lateral SACM Ge-on-Si APD on a silicon-on-insulator (SOI) wafer, featuring a 10 μm-long, 0.5 μm-wide Ge layer at 1310 nm on a standard 8-inch silicon photonics platform. The dark current measures approximately 38.6 μA at −21 V, indicating a breakdown voltage greater than −21 V for the device. The APDs exhibit a unit-gain responsivity of 0.5 A/W at −10 V. At −15 V, their responsivity reaches 2.98 and 2.91 A/W with input powers of −10 and −25 dBm, respectively. The device's 3-dB bandwidth is 15 GHz with an input power of −15 dBm and a gain is 11.68. Experimental results show a peak in impedance at high bias voltages, attributed to inductor and capacitor (LC) circuit resonance, enhancing frequency response. Furthermore, 20 Gbps eye diagrams at −21 V and −9 dBm input power reveal signal to noise ratio (SNRs) of 5.30. This lateral SACM APD, compatible with the stand complementary metal oxide semiconductor (CMOS) process, shows that utilizing the peaking effect at low optical power increases bandwidth.

We demonstrated a scheme of phase-locked terahertz quantum cascade lasers (THz QCLs) array, with a single-mode pulse power of 108 mW at 13 K. The device utilizes a Talbot cavity to achieve phase locking among five ridge lasers with first-order buried distributed feedback (DFB) grating, resulting in nearly five times amplification of the single-mode power. Due to the optimum length of Talbot cavity depends on wavelength, the combination of Talbot cavity with the DFB grating leads to better power amplification than the combination with multimode Fabry−Perot (F−P) cavities. The Talbot cavity facet reflects light back to the ridge array direction and achieves self-imaging in the array, enabling phase-locked operation of ridges. We set the spacing between adjacent elements to be 220 μm, much larger than the free-space wavelength, ensuring the operation of the fundamental supermode throughout the laser's dynamic range and obtaining a high-brightness far-field distribution. This scheme provides a new approach for enhancing the single-mode power of THz QCLs.

Enhancement-mode (E-mode) GaN-on-Si radio-frequency (RF) high-electron-mobility transistors (HEMTs) were fabricated on an ultrathin-barrier (UTB) AlGaN (< 6 nm)/GaN heterostructure featuring a naturally depleted 2-D electron gas (2DEG) channel. The fabricated E-mode HEMTs exhibit a relatively high threshold voltage (V_TH) of +1.1 V with good uniformity. A maximum current/power gain cut-off frequency (f_T/f_MAX) of 31.3/99.6 GHz with a power added efficiency (PAE) of 52.47% and an output power density (P_out) of 1.0 W/mm at 3.5 GHz were achieved on the fabricated E-mode HEMTs with 1-µm gate and Au-free ohmic contact.

Memtransistors in which the source−drain channel conductance can be nonvolatilely manipulated through the gate signals have emerged as promising components for implementing neuromorphic computing. On the other side, it is known that the complementary metal-oxide-semiconductor (CMOS) field effect transistors have played the fundamental role in the modern integrated circuit technology. Therefore, will complementary memtransistors (CMT) also play such a role in the future neuromorphic circuits and chips? In this review, various types of materials and physical mechanisms for constructing CMT (how) are inspected with their merits and need-to-address challenges discussed. Then the unique properties (what) and potential applications of CMT in different learning algorithms/scenarios of spiking neural networks (why) are reviewed, including supervised rule, reinforcement one, dynamic vision with in-sensor computing, etc. Through exploiting the complementary structure-related novel functions, significant reduction of hardware consuming, enhancement of energy/efficiency ratio and other advantages have been gained, illustrating the alluring prospect of design technology co-optimization (DTCO) of CMT towards neuromorphic computing.

In–Ga–Zn–O (IGZO) channel based thin-film transistors (TFT), which exhibit high on–off current ratio and relatively high mobility, has been widely researched due to its back end of line (BEOL)-compatible potential for the next generation dynamic random access memory (DRAM) application. In this work, thermal atomic layer deposition (TALD) indium gallium zinc oxide (IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition (ALD) process. In addition, thin-film transistors (TFTs) with vertical channel-all-around (CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Electrochemical impedance spectroscopy (EIS) flow cytometry offers the advantages of speed, affordability, and portability in cell analysis and cytometry applications. However, the integration challenges of microfluidic and EIS read-out circuits hinder the downsizing of cytometry devices. To address this, we developed a thermal-bubble-driven impedance flow cytometric application-specific integrated circuit (ASIC). The thermal-bubble micropump avoids external piping and equipment, enabling high-throughput designs. With a total of 36 cell counting channels, each measuring 884 × 220 μm², the chip significantly enhances the throughput of flow cytometers. Each cell counting channel incorporates a differential trans-impedance amplifier (TIA) to amplify weak biosensing signals. By eliminating the parasitic parameters created at the complementary metal-oxide-semiconductor transistor (CMOS)-micro-electromechanical systems (MEMS) interface, the counting accuracy can be increased. The on-chip TIA can adjust feedback resistance from 5 to 60 kΩ to accommodate solutions with different impedances. The chip effectively classifies particles of varying sizes, demonstrated by the average peak voltages of 0.0529 and 0.4510 mV for 7 and 14 μm polystyrene beads, respectively. Moreover, the counting accuracies of the chip for polystyrene beads and MSTO-211H cells are both greater than 97.6%. The chip exhibits potential for impedance flow cytometer at low cost, high-throughput, and miniaturization for the application of point-of-care diagnostics.

There are challenges to the reliability evaluation for insulated gate bipolar transistors (IGBT) on electric vehicles, such as junction temperature measurement, computational and storage resources. In this paper, a junction temperature estimation approach based on neural network without additional cost is proposed and the lifetime calculation for IGBT using electric vehicle big data is performed. The direct current (DC) voltage, operation current, switching frequency, negative thermal coefficient thermistor (NTC) temperature and IGBT lifetime are inputs. And the junction temperature (T_j) is output. With the rain flow counting method, the classified irregular temperatures are brought into the life model for the failure cycles. The fatigue accumulation method is then used to calculate the IGBT lifetime. To solve the limited computational and storage resources of electric vehicle controllers, the operation of IGBT lifetime calculation is running on a big data platform. The lifetime is then transmitted wirelessly to electric vehicles as input for neural network. Thus the junction temperature of IGBT under long-term operating conditions can be accurately estimated. A test platform of the motor controller combined with the vehicle big data server is built for the IGBT accelerated aging test. Subsequently, the IGBT lifetime predictions are derived from the junction temperature estimation by the neural network method and the thermal network method. The experiment shows that the lifetime prediction based on a neural network with big data demonstrates a higher accuracy than that of the thermal network, which improves the reliability evaluation of system.

The flexible perovskite light-emitting diodes (FPeLEDs), which can be expediently integrated to portable and wearable devices, have shown great potential in various applications. The FPeLEDs inherit the unique optical properties of metal halide perovskites, such as tunable bandgap, narrow emission linewidth, high photoluminescence quantum yield, and particularly, the soft nature of lattice. At present, substantial efforts have been made for FPeLEDs with encouraging external quantum efficiency (EQE) of 24.5%. Herein, we summarize the recent progress in FPeLEDs, focusing on the strategy developed for perovskite emission layers and flexible electrodes to facilitate the optoelectrical and mechanical performance. In addition, we present relevant applications of FPeLEDs in displays and beyond. Finally, perspective toward the future development and applications of flexible PeLEDs are also discussed.