Concept and design of super junction devices

    Corresponding author: Bo Zhang,
  • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

Key words: super junctionsilicon limitpower semiconductor devicedesign theory

Abstract: The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of RonVB2.5, showing a quasi-linear relationship of RonVB1.03.


1.   Introduction
  • The power MOSFET may be treated as a composite structure of the low-voltage MOS and the voltage-sustaining layer (VSL)[1]. The basic requirement of the VSL is both high breakdown voltage VB and low specific on-resistance Ron. Generally, the former requires a lightly doped and thick (long for lateral devices) VSL and the latter always needs a highly doped and thin (short for lateral devices) VSL. The best trade-off between Ron and VB is realized by the optimization of the proper doping concentration and structure of the VSL. For the power MOSFET, the Ron and VB relationship satisfies the “silicon limit” of RonVB2.5[2]. To alleviate this contradiction, Chen X B proposed several methods to introduce the high electric field in the bulk of the device, including a new structure called SJ now[35], as shown in Fig. 1. Other researchers also developed similar concepts, e.g., Coe proposed the interdigitated SJ structure[6] and Tihanyi also obtained a similar structure[7].

    The concept of “super junction” was introduced by Fujihira in 1997[8]. The first realization of the power MOSFET based on the SJ concept was the CoolMOS fabricated in 1998 by Siemens AG, i. e., Infineon now, realizing Ron of 35 mΩ·cm2 for the 600 V device[9]. Because the new device realizes a remarkable Ron reduction while keeping almost all of the advantages of the power MOSFET, the SJ has been recognized as the “milestone of the power MOSFET”[10]. With the development of the process, the 600–900 V power SJ MOSFET devices have realized the commercial production in Infineon, IR, Toshiba, Fairchild, STM Microelectronics, Micro Semi, Ixys, Fuji Electric, ON Semi, Renesas, Electronics, NXP, Huahong and Hangzhou Silan, and so on.

    It should be pointed out that the SJ is an innovation of the VSL, therefore, the SJ can be used in not only the vertical MOSFET but also other power devices, e.g., the key device of the power integrated circuit—LDMOS (laterally double-diffused MOSFET). So it is important to review the development and forecast the future of the SJ for different aspects. This paper firstly introduces the basic concepts of the SJ and gives the development of the characteristics, process and new structures of the SJ devices. Then an optimization theory of both the vertical and lateral SJ devices is discussed. Lastly, this paper gives the prospects of the development direction and analytical theory of the SJ concept.

2.   Concept of SJ
  • The most significant difference between the conventional VSL and the SJ VSL is a series of lateral junctions between the N and the P regions being introduced into the VSL, which leads to the lateral depletion effect inside the VSL. Therefore, the SJ is a typical junction-type VSL (J-VSL) and the conventional VSL is a typical resistance-type VSL (R-VSL). It is a qualitative change of the VSL from the R-VSL to the J-VSL, which brings some new concepts as follows.

  • 2.1.   Charge and potential electric fields

  • It is a qualitative change of the VSL from the R-VSL to the J-VSL. The charges with equal magnitude, but opposite polarity, are introduced into the J-VSL to ensure the charge balance. This change results in the remarkable lateral component of the electric field caused by the ionized charges, which is an embodiment of the bulk electric field optimization.

    To analyze the modulation of the electric field from the ionized charges to the electric field caused by the applied voltage, the charge electric field Eq(x, y) and potential electric field Ep(y) of the SJ are defined and shown in Fig. 2, in which the width, length and doping concentration of the N and P regions are W, Ld and N, respectively.

    The explanation of the electric field E(x, y) of the SJ includes two aspects:

    Physically, E(x, y) is a superposition of two components Ep(y) and Eq(x, y). The Ep(y) is the potential electric field caused by the applied voltage, which is a constant in the SJ region only having the 1-D y-component. The Eq(x, y) is the charge electric field caused by the ionized charges of N and P regions, which has both the 2-D x- and y-components.

    Mathematically, E(x, y) can be given by solving the Poisson equation with two parts: the Laplace equation ${\nabla ^2}\varphi \,\,{\rm{ = 0}}$ with the boundary conditions of VB at drain and zero potential at source to give Ep = VB/Ld; the Poisson equation ${\nabla ^2}\phi \,\,{\rm{ = }} - \rho /{\varepsilon _{\rm s}}$ with zero potentials at both source and drain to determine Eq(x, y), where ϕ and φ are the potentials, ρ and εs are the charge density and the dielectric constant of the silicon, respectively.

    Therefore, E(x, y) is expressed with the 1-D potential field and the 2-D charge field:

    where ${{ E}_{\rm{q}}}(x, y) = {{ E}_{{\rm{q, x}}}}(x, y) + {{ E}_{{\rm{q, y}}}}(x, y)$ is the 2-D charge electric field with $E_{\rm q} $ , x(x, y) and $E_{\rm q} $ , y(x, y) being the x- and y-components.

  • 2.2.   Equal-potential relationship caused by Eq(x, y)

  • It was found that the equal-potential relationship is satisfied in the SJ structure[11], as shown in Fig. 3. The relationship means that the integral value of Eq(0, y) from 0 to Ld/2 is equal to that of Eq(x, 0) from 0 to W/2, which also leads to the peak electric fields at point O' and A are E0 = 7.6 × 10−12 NW and Eq = 5.6 × 10−12 NW, respectively. The equal-potential relationship reveals an important result of the SJ: the vertical and lateral peak electric fields of Eq(x, y) are only related to the lateral dose NW of the SJ and independent to Ld. Therefore, the high field region of the vertical component of Eq(x, y) is determined by its lateral component. The impact of the doping concentration on the surface electric field is confined in the regions near points A and B with a length about 0.78 W[11]. The vertical electric field in the bulk of the SJ can roughly be considered as a uniform electric field because the condition of W << Ld is always satisfied. This is the modulation result of Eq(x, y) to Ep.

3.   Development of SJ

    3.1.   Development of the characteristics

  • For a given VB, Ron of the SJ MOSFET is much lower than that of the VDMOS (vertical double-diffused MOSFET) and shows more advantages for the high-voltage application. The SJ devices have been widely researched in the range from 30 to 1000 even 1200 V. Partial experiments are shown in Fig. 4. For the SJ devices with VB lower than 100 V, the optimized device was obtained by shrinking the cell pitch with the width of the P-regions only 0.7 to 1 μm[12]. For the SJ devices with VB from 100 to 500 V, the optimized result was realized by the trench epitaxy process with the high aspect ratio[13]. For the SJ devices with VB over 500 V, the optimized device of the multi-epitaxy was obtained by implanting both the N and P regions in a 12 μm cell pitch and the optimized device with the trench filling process was realized by shrinking the widths of the P and N regions to only 1.3 and 1.7 μm[14, 15].

    It is very obvious that the SJ concept breaks the “silicon limit” in different voltage levels. For example, the device in Ref. [15] obtained Ron of only 7.8 mΩ·cm2 with VB of 685 V. The corresponding Ron from the “silicon limit” is 101.9 mΩ·cm2. Ron of the SJ is reduced by one order of magnitude. The advantage of the “milestone” device is demonstrated definitely.

  • 3.2.   Development of the process

  • The process difficulty of the SJ is how to realize the P regions in the N-type silicon because most of the processes in the field of microelectronic devices are the surface processes. There are three typical processes to realize the SJ: (1) the multi-epitaxy process: the P regions of the SJ are realized by the P-type doping for each epitaxy process or both the P- and N-type regions are realized within the intrinsic epitaxy process; (2) the trench process: the deep trench is etched in the N-type region and the P regions can be realized by the P-type epitaxy filling process or the side-wall doping process, where the N-type doping can also be introduced in the sidewall; (3) the multidoping process: the P-type region is realized by multidoping with different implantation energies. The first process to realized SJ is the multi-epitaxy process shown in Fig. 5(a)[9, 31, 41, 42], which requires the charge balance between the ionized positive charges in the N region and the negative net charges in the P region after the compensation. The second process shown in Fig. 5(b)[4345] can achieve an exact charge balance by controlling the implant dose and the width of implantation windows of both N and P regions, thus a better uniformity is realized. However, the second process needs an additional mask and implantations of the N region. The SJ structure realized by the trench process shown in Figs. 5(d)5(g)[13, 15, 26, 28, 46] can obtain the smaller aspect ratio than that by the multi-epitaxy process.

    The trench process simultaneously implements more uniform doping distribution of both N and P regions so that it is more useful to reduce Ron. As the depth of the ion implant increases with the implantation energy, the SJ may be realized by using the multidoping process shown in Fig. 5(c)[12, 17, 19]. This process is generally used in the SJ VDMOS with the VB of 30–100 V. It achieves the J-VSL length of 2.5–3 μm with the maximum implantation energy of 1.5–2 MeV. Furthermore, the energy of 25 MeV can also be used to realize the SJ with VB of 550 V, and the special mask with the difficult fabrication process is also needed[30].

  • 3.3.   Development of the structures

  • The structures of the SJ devices can be divided into two categories, namely, the vertical SJ devices and the lateral SJ devices. Fig. 6 gives the vertical devices based on the SJ concept. The semi-SJ VDMOS[4749] was proposed to relieve the process difficulty, in which the VSL consists of a J-VSL with the thickness of tSJ and an R-VSL with the thickness of tBAL, making full use of the low Ron advantage of the SJ structure with a simpler process. The SJ IGBT (insulated gate bipolar transistor)[50] was realized by introducing the SJ into the conventional FS IGBT. Similar to the VDMOS device, VB of SJ IGBT is higher than that of the traditional IGBT with the same drift length and the device shows a better characteristic in both the low and high doping ranges.

    In the SJ VDMOS, a large number of carriers are stored in the P and N regions, resulting in the high reverse recovery charge, high EMI noise and high power consumption. The SJ VDMOS with a Schottky contact shown in Fig. 6(c)[51] was proposed to solve that problem. It can make the recovery charge of the diode reduce by 58% under the same current condition. Meantime, the SJ concept was introduced into the junction barrier Schottky rectifier (JBS) and Schottky barrier diode (SBD) devices to obtain the lower forward voltage and higher current density described in Figs. 6(d)6(e)[52]. Besides, the trench SJ SBD shown in the right of Fig. 6(d) realized a reduction of the reverse current by 46.7% compared with the planar SJ SBD. Another difficulty in the SJ fabrication process is the impurity diffusion between the N/P regions. The oxide-by-passed SJ VDMOS (OB SJ VDMOS) was presented to avoid that problem, as shown in Fig. 6(f)[53]. The oxide layer not only effectively stops the diffusion but also introduces the depletion effect to reduce Ron. The HK dielectric can introduce the polarization charges into the VSL, as shown in Figs. 6(g) and 6(h)[54, 55], respectively. The new charge balance between the charges by the HK dielectric layer and the ionized charges are realized in the HK devices.

    The SJ concept has also been introduced into the lateral devices and widely researched on both the SOI-based and the silicon-based materials, the essence of which is reducing the conduction loss.

    The lateral SJ devices have been an important development direction in the field of the high voltage power integrated technology. However, the substrate-assisted depletion (SAD) effect reduces the vertical breakdown voltage of the lateral SJ devices[56]. The lateral SJ may be realized by a CMOS-compatible process with both the N- and P-type implantations. The first experimental implementation of the surface SJ with the two type implantations and the analytical model of the SAD effect were developed by authors in Refs. [57, 58], respectively. The typical lateral SJ devices are shown in Fig. 7. The CBSLOP LDMOS was proposed to alleviate the SAD effect with a surface SJ layer[56]. The SJ layer provides a low resistance current path, which experimentally realized VB of 500 V and Ron of 96 mΩ·cm2.

    Fig. 7(b) shows the SJ LDMOS on the sapphire substrate[59], which uses an insulating substrate to eliminate the SAD effect. But the application of this device was limited by its high material cost and bad interface characteristic. Fig. 7(c) gives the unbalanced SJ device with the gradually increased width of N region and the decreased width of P region from source to drain to accommodate the enhancement of SAD effect[60]. Fig. 7(d) illustrates the partial SJ LDMOS with the single N-type R-VSL near the drain[61]. The SAD effect is alleviated by the RESURF (reduced surface field) effect. Similarly, an N-type buffer layer was introduced under the SJ layer of the SJ LDMOS, shown in Fig. 7(e)[62], to achieve the same purpose. Fig. 7(f) shows a new structure of SJ LDMOS with the non-uniform N-buried layer[63]. The width of the non-uniform doping N-buried layer increases from source to drain to obtain higher VB. Based on the same concept mentioned in Fig. 7(f), the new device with step doping buried layer shown in Fig. 7(g) optimized the surface electric field by introducing the new electric field peak in the drift region[64]. Fig. 7(h) shows the SJ LDMOS with the surface step doped N layer on the SOI base[65]. The surface step doped N layer compensates the charge imbalance caused by SAD effect. Fig. 7(i) gives another method to weaken the SAD effect by realizing the charge compensation through the partial ionization of N+/P+ on both sides of the dielectric trench[66].

    The series of inner PN junctions of the J-VSL also play an important role in the transient characteristics of the SJ devices[67]. The equal potential lines of the SJ in the turn-on and turn-off processes are shown in Fig. 8. The on-state charge electric field Eq, on of the inner PN junctions causes the potential of the neutral zone in the N region ϕN higher than ϕP in the P region.

    For the turn-on process in Fig. 8(a), the condition ϕN > 0 > ϕP is satisfied and thus the electrons and holes flow from the source to the drain because of the different directions of the electric fields Ee and Eh in the neutral zones of N region and P region, respectively. This movement in the same direction of both the electrons and holes results in a short turn-on duration time of the nanosecond order for the SJ devices. For the turn-off process in Fig. 8(b), the condition ϕN > ϕP > 0 is satisfied and thus the electrons flow from the source to the drain and holes flow along the opposite direction, which leads to a delay time caused by the inner junction capacitance. Then a fast fall time is observed with most of the J-VSL being depleted. Please note that the turn-off loss of the SJ devices has no obvious increase because this stage shows a low drain voltage Vd determined by the lateral PN junctions. In summary, the special carrier movement and the effect of the additional junction capacitance should be considered in the transient characteristics of the SJ devices.

4.   Breakthrough of the conventional “silicon limit”
  • After the SJ was invented, the devices based on the SJ concept were firstly optimized with the 1-D models[8, 40], in which the SJ was treated as the 1-D PIN in the vertical direction and the 1-D PN junction in the lateral direction. The analytical 2-D electric field distribution of the SJ was firstly developed based on the Fourier series expansion of the ionized charges[5, 41]. Another method was proposed by solving the Poisson equation in both the N and P regions[69]. The authors also proposed a new Taylor series method to obtain the 2-D electric field of the SJ[70].

    The SJ shows a complex 2-D electric field distribution because of the qualitative change of the J-VSL and it is difficult to theoretically obtain the RonVB relationship of the SJ device. The exact full depletion state is considered as the optimized condition of the SJ. Chen X B et al theoretically demonstrated the RonVB relationship of the SJ at this condition[5]:

    in which g is a constant depending on the cell pattern and W is in micron.

    The Ron reduction of the SJ MOS is determined by two aspects: (1) the exponential value is reduced from 2.5 to 1.32 by the interruption of the strong dependence between the on-state carrier and the surface electric field; (2) the constant factor C in the conventional RonVB relationship becomes a pillar-width- and cell-pattern-dependent factor because of the bulk junction depletion of the J-VSL. Therefore, Ron of the SJ can be further reduced by the process such as shrinking the cell pitch. Furthermore, the minimum Ron is searched for both the vertical and lateral SJ devices.

  • 4.1.   Non-full depletion mode

  • The PIN has the unique and highest breakdown voltage VB0 for a given Ld. Therefore, VB0 may be chosen as a measurement of VB of the SJ device with the same Ld. The VB normalization method was proposed in Ref. [11] by normalizing VB with VB0. The normalized factor is defined as η = VB/VB0. η is obtained as:

    in which γ = ET/Ep is the electric field factor and F(γ) is a power function given in Ref. [11].

    Fig. 9(a) shows η as functions of γ with different Ld/W and the simulated results are also given. η is reduced with γ for the same Ld/W, which reflects the impact of Eq(x, y) to VB. The exact depletion state of the SJ corresponds to the condition that electric fields of points A' and B' are zero at breakdown, i.e., γ = 1 in Fig. 9(a). As a result, γ differentiates the breakdown state of the SJ into three regions: (1) γ = 0 corresponding to the PIN; (2) 0 < γ ≤ 1 corresponding to the full depletion (FD) mode with the full depleted VSL; (3) γ > 1 corresponding to the non-full depletion (NFD) mode. VB of the SJ in the NFD mode can sustain VB over 80% of VB0. Fig. 9(b) gives the physical image of the SJ structure in the NFD mode. δ shown in the dashed box is the length of the neutral region in each pillar at breakdown. If the neutral region exists at breakdown condition (δ > 0), the SJ structure is in the NFD mode. Otherwise, it is in the FD mode. The NFD SJ is realized by increasing the doping density NW of the N and P regions simultaneously and thus may realize the lower Ron under the given VB.

  • 4.2.   Ron, min method based on global optimization

  • If we obtain all the breakdown states of the SJ under the given W and VB, the state corresponding to the minimum Ron can be found as an optimization result. Based on this global optimization concept[68, 71], we can drain the pond to get all the fish including the maximum one, i. e., the Ron, min of the SJ. From the mode analysis, the effect of Eq(x, y) on VB is discussed and the Ron, min may be realized in the NFD mode. N and Ld are the two parameters determining Ron of the SJ. The increased N leads to the higher Eq(x, y) and thus the longer Ld is needed to sustain the same VB. However, the higher N and the longer Ld have the opposite impacts on Ron.

    Fig. 10 shows the breakdown path COC' and electric field along the path of the SJ. To realize the Ron, min, the one-to-one relationship between any given N and Ld should be obtained in the range from 0 to Nmax, in which the breakdown state of the SJ is calculated with the breakdown criterion ∫ α ds = 1[70] to give the N, Ld and Ron. Ron of the SJ shows a U-shape well distribution, called the R-well[71], and the only Ron, min is obtained at the optimized doping concentration Nopt. Because all the possible optimization points for the SJ with given W and VB are located exactly at the R-well, all the points can be searched along the R-well with different optimizing strategies[71]. The target of the global optimization is to search the Ron, min. Fig. 11 shows the R-wells of both the SJ device and the device with the interface isolator (I-SJ).

    The different optimizations may be described with the constant η or γ: η = constant is for the Ron, min optimization and γ = constant is for other optimizations. From the optimization method, the design formulas are obtained[71].

    For the Ron, min condition in the NFD mode:

    For the γ = 1 condition in the FD mode:

    in which $a = {(1 + 903W/{V_B}^{7/6})^{ - 1/7}}$ is a factor determined by W and VB.

    The RonVB expressions of the SJ under the η = constant and the γ = constant conditions had been demonstrated in Ref. [11]. The relationships in both the NFD and the FD modes are thus calculated from Eqs. (4) and (5) with the consideration of the JFET effect[73].

    For the Ron, min condition in the NFD mode:

    For the γ = 1 condition in the FD mode:

    It is shown that Ron of the SJ is dependent on both W and VB. The device with the narrower W has the lower Ron and therefore the development of the SJ may be simply treated as the development of the process to realize the narrow cell pitch.

    Fig. 12 gives the comparison of RonVB relationships between the Ron, min optimization and other optimizations. It is found that the Ron, min optimization realizes the RonVB1.03 relationship with η being constant compared with RonVB1.32 for other optimizations with γ being constants. We think the quasi-linear relationship of RonVB1.03 may be the minimum one for the balanced symmetric SJ devices, which is much lower than the conventional RonVB2.5[23].

  • 4.3.   Equivalent substrate model of the lateral SJ

  • From the section 3.3, the optimization of the lateral SJ device mainly focuses on two aspects: (1) the VB optimization, i.e., the suppression of the SAD effect; (2) the Ron optimization, e.g., the dose of NW = 2 × 1012 cm−2 by analogy with the typical RESURF condition[61]. The equivalent substrate (ES) model described the analytical VB optimization of the lateral SJ[58].

    The concept of the ES model is given in Fig. 13. To analyze the impact of the ES on the surface SJ layer, the charge compensation layer (CCL) and the depleted substrate region are defined as the ES, which is treated as a whole to analyze its electric field modulation of the surface SJ layer, as shown in Fig. 13(b). The ES model reveals the essence of the SAD effect: the charge balance between the N- and P-regions is interrupted due to ionized negative charges of the P-sub, which leads to the nonfull depletion of the P-pillars and a decreased VB of the conventional lateral SJ. If the SAD effect is fully eliminated, the optimized lateral SJ has a similar VB compared with that of the vertical SJ with the same Ld, as shown in Fig. 13(c).

    The SAD effect can be eliminated by the optimized substrate conditions theoretically[58].

    (1) Electrical neutrality, i.e., the equivalent charge density QES of the ES is zero:

    which shows that the optimized ES is quasi electrical neutral and can be treated as an intrinsic layer. Then, the charge balance of SJ layer is realized by the charge balance of the ES.

    (2) Uniform surface electric field EES of the ES:

    which means the uniform surface electric field of the ES, avoiding the premature breakdown.

    For the lateral SJ device satisfying the optimized substrate conditions, the R-well distribution is also found and used to give the Ron, min. The design formulas and RonVB relationship of the lateral SJ are obtained based on the R-well and given as[68]:

    in which W and H are in micron.

    The optimization results from Eq. (10) are compared with other SJ-LDMOS devices, as shown in Fig. 14. The simulations, located at the trend lines from Eq. (10), show that the devices designed with the proposed formulas have the lowest Ron for all the cases. By comparing N and Ld to those results from Eq. (10), the devices can be divided into three groups: (1) with the similar Ld and N, and thus realize the optimiz- ations[56, 64, 74, 75]. In this case, the Ron performances have no significant differences; (2) with the similar Ld only, indicating that the SAD effect have been suppressed effectively[76]; (3) with both the longer Ld and lower N, as given in Refs. [61, 7779]. The larger improvements of Ron may be observed in the last two cases because of two reasons: firstly, the optimized N is much higher than those in the comparative references, e. g., being up to almost 2.5 times for the device with W of 1 μm[61]. Secondly, a longer Ld may be necessary especially for the high voltage devices to avoid the premature breakdown caused by the small curvature radius[78, 79]. Recently, the authors proposed and experimentally demonstrated a novel SJ-LDMOS with a thin layer SOI[80] by using the SOI-based ES model and formula (10), which exhibits an Ron of 145 mΩ·cm2 with a high VB of 977 V, realizing the highest experimental VB among the SJ-LDMOS devices up to now.

5.   Conclusion and prospect
  • As the most important innovation of the VSL, the SJ plays an important role in the power semiconductor devices. The qualitative change from the R-VSL to the J-VSL causes the 2-D charge electric field modulation effect to optimize the bulk electric field. The development of the SJ mostly focuses on the process and the new structures. Based on the global optimization, the SJ device can be optimized with the theory including the NFD model, the Ron, min optimization method and the ES model. The SJ realizes the new quasi-linear relationship of RonVB1.03.

    It is found that Ron of the experimental SJ devices can be further reduced by 20%–40% with W from 5–10 μm and 60%–80% with W from 1–4 μm. Therefore, there is a big development space to obtain the lower Ron in the experiments by using the narrower cell and higher doping concentration. However, the JFET effect and the Zener breakdown between the inner PN junctions of the SJ may cause a strong characteristic degradation if W is lower than 0.5 μm. The SJ concept can also be applied to the devices based on other semiconductor materials, such as the SiC[81, 82] and the GaN[83, 84]. The optimization theory of the SJ based on the silicon is universal for other materials, in which the differences of the impact ionized rate (band gap), the mobility and the dielectric constant should be considered. The RonVB relationship for other materials may show the similar indexes and efficiently reduced coefficients, e.g., coefficient is reduced by more than two orders of magnitude for the SiC SJ devices. The outstanding potential of the SJ concept are very obvious for these new materials, however, more challenges are faced including the high-quality material preparation, special process and reliability, and so on. Besides, the charge balance from the SJ has also been extended to other charge forms, e.g., the charge balanced 2-D electron and hole gases[84].

Figure (14)  Reference (84) Relative (20)

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