With the increase of ESD ion implantation dose, the breakdown voltage of drain and body is reduced, which is conducive to the uniform opening of LNPN parasitic triode and the simultaneous opening of GGNMOS fingers[15, 16], which reduces the current density per unit area and keeps the lattice temperature lower under the same ESD current. In turn, more ESD current can be released under the same lattice temperature.
When the width of single finger is small, the ESD capacity increases linearly with the increase of width. When it reaches 42 μm, it basically reaches the maximum value of discharge efficiency per unit size. When the width of single finger continues to increase, the ESD discharge current can continue to increase, but the increased part cannot be effectively triggered, and the comprehensive discharge efficiency shows a downward trend. Therefore, a more effective method is to mirror a GGNMOS to increase the ESD discharge capacity.
When the ESD implant dose is 6 × 1013 cm–2, and the number of multi fingers is less than 8, the robustness of GGNMOS is poor, and its ESD discharge efficiency is at a low level. The main reason is that the body contact is relatively good. After large injection, the large area source body junction cannot be forwarded. The large ESD current in the central area causes lattice burnout. When the number of multi fingers is more than 8, the area of the triggered central area increases, the ESD current per unit area decreases and more current can be released before the lattice burns down.
In the same GGNMOS device layout, compared with the traditional bulk silicon CMOS technology, the introduction of epitaxial layer increases the state of body contact and leads to the degeneration of ESD performance. In the GGNMOS structure as shown in Fig. 5(b), when the ESD event comes, the drain end will generate PN junction breakdown, and a large number of hole carriers will be injected into the body region (pwell, p-epi, p+ sub). Due to the introduction of p+ sub, the current in the z-axis direction will increase, but due to the decrease of resistance, the body potential cannot reach the previous level under the same hole carrier injection condition. In addition, the introduction of p+ sub reduces the transverse parasitic resistance, reduces the barrier voltage drop in the x-axis and y-axis direction to a range of 0.6–0.7 V (as shown in the ring area in Fig. 5(a)), and finally reduces the ability of the whole GGNMOS to release current in ESD events. By increasing the single finger width (y-axis direction), the hole carrier injection current is increased, the barrier voltage drop is increased to 0.6–0.7 V, the width near the contact area of the outer P+ ring (body in Fig. 5(b)) that can not effectively start the LNPN (as shown in the letter S in Fig. 5(a)), and the discharge efficiency of GGNMOS device is increased.
When the DCGS value increases from 1.5 μm, the reverse biased drain junction capacitance at the drain end under the forward ESD stress will increase, and the parasitic resistance at the drain end will increase, which will help to expand the ESD current distribution along the single finger width more evenly, which is shown as the increase of the ESD discharge capacity. When the DCGS value reaches 2.3 μm, increasing the size will lead to the increase of the drain parasitic resistance, showing a significant voltage drop. As a result, the voltage on the gate oxide layer at the input is increased, and this trend becomes more obvious as the DCGS value continues to increase, resulting in the overall GGNMOS ESD capability decline.
Through these simulations and experimental TLP tests, it is necessary to combine the gate length, single finger width, multi finger number, DCGS, ESD ion implantation and other factors of GGNMOS. These factors are interactive and need further experimental design to optimize ESD performance. In addition, good ESD protection quality also includes several parameters that need to be considered in application, such as capacitance, leakage current, power sequencing and overvoltage conditioning etc. The ESD device or clamp should not have too much capacitance that it violates the loading limits of the I/O signaling specification. It must not draw excessive current at either high or low input or output levels. In addition, it must be compatible with normal sequence for applying power, and it can survive for a period of time under the condition of over voltage. Therefore, test structures for benchmarking the ESD robustness of different CMOS process, so as to get an excellent ESD capability.
Compared with the ESD performance of GGNMOS devices found in the relevant literature, the performance of GGNMOS devices finally achieved in this work has achieved a good level, the discharge efficiency of 3.3 V GGNMOS is 12.08 mA/μm, and 1.8 V GGNMOS is 16 mA/μm. The details are shown in Table 2.