A 0.13μm Mixed-Signal CMOS High Speed USB 2.0 Transceiver

  • State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
  • State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
  • State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
  • State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

Key words: differential envelope detectorphase locked looploop filtercommon mode feedback

Abstract: A USB 2.0 high speed transceiver was designed in 0.13μm mixed-signal CMOS technology.A high-speed current-mode differential comparator,a phase detector with window-enabling logic,and an analog continuously-adjusting CMFB were developed to meet the specifications and 0.13μm technology.The transceiver has been fabricated in SMIC.The transmitter jitter was 53ps,and the bit error rate of the receiver was less than 1e-12.The power consumption was 42.5mW at a power supply of 1.2V, and the chip area was 900μm×700μm.

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